Patents by Inventor Shimin SUN

Shimin SUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200241369
    Abstract: A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes: a signal line; a common electrode line an extension direction of which is same as an extension direction of the signal line; a transistor including a semiconductor layer which includes a source region and a drain region; a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and a second storage electrode which is connected with the common electrode line and is insulated from the first storage electrode. In the pixel structure, portions, between the signal line and the common electrode line, of the first storage electrode and the second storage electrode includes overlap with each other to form a first storage capacitance.
    Type: Application
    Filed: August 7, 2017
    Publication date: July 30, 2020
    Inventors: Duolong DING, Huafeng LIU, Shengwei ZHAO, Chaochao SUN, Chao WANG, Jingping LV, Meng YANG, Lei YANG, Chongliang HU, Lin XIE, Bule SHUN, Shimin SUN
  • Patent number: 10564772
    Abstract: The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: February 18, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Chaochao Sun, Huafeng Liu, Shengwei Zhao, Kai Zhang, Lei Yang, Lulu Ye, Jingping Lv, Chao Wang, Chongliang Hu, Meng Yang, Duolong Ding, Bule Shun, Lin Xie, Yao Li, Shimin Sun
  • Patent number: 10325943
    Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 18, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Chaochao Sun, Chao Wang, Huafeng Liu, Shengwei Zhao, Bule Shun, Lei Yang, Chongliang Hu, Meng Yang, Jingping Lv, Lin Xie, Shimin Sun, Duolong Ding
  • Publication number: 20180197901
    Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.
    Type: Application
    Filed: December 12, 2016
    Publication date: July 12, 2018
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Chaochao Sun, Chao Wang, Huafeng Liu, Shengwei Zhao, Bule Shun, Lei Yang, Chongliang Hu, Meng Yang, Jingping Lv, Lin Xie, Shimin Sun, Duolong Ding
  • Publication number: 20170205953
    Abstract: The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.
    Type: Application
    Filed: August 10, 2016
    Publication date: July 20, 2017
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Chaochao SUN, Huafeng LIU, Shengwei ZHAO, Kai ZHANG, Lei YANG, Lulu YE, Jingping LV, Chao WANG, Chongliang HU, Meng YANG, Duolong DING, Bule SHUN, Lin XIE, Yao LI, Shimin SUN