Abstract: An integrator having an offset evaluation circuit and a collected charge reduction circuitry and method for using the integrator. The integrator includes an amplifier, operable to amplify an input signal, an integration capacitor for collecting charge indicative of a level of the input signal and an offset capacitor. The offset evaluation circuit is operable to charge the offset capacitor with charge corresponding to an offset voltage of the amplifier and the collected charge reduction circuitry is operable to collect charge resulting from disconnection of the offset evaluation circuit, thereby reducing an amount of charge and associated noise input to the amplifier.

Abstract: An integrator having an offset evaluation circuit and a collected charge reduction circuitry and method for using the integrator. The integrator includes an amplifier, operable to amplify an input signal, an integration capacitor for collecting charge indicative of a level of the input signal and an offset capacitor. The offset evaluation circuit is operable to charge the offset capacitor with charge corresponding to an offset voltage of the amplifier and the collected charge reduction circuitry is operable to collect charge resulting from disconnection of the offset evaluation circuit, thereby reducing an amount of charge and associated noise input to the amplifier.

Abstract: A pixel readout circuit for use with an imaging pixel array, comprising: an input channel for receiving an image signal corresponding to an electrical output of a photosensitive element of the pixel; and an electronic circuit interconnected between an input channel and an output readout utility. The electronic circuit comprises a capacitive unit, and a single analyzer. The capacitive unit is controllably linked to the input channel for accumulating a charge corresponding to received intensity generated by the pixel during a single frame period, and is connected to the output readout utility.

Abstract: A pixel readout circuit for use with an imaging pixel array, comprising: an input channel for receiving an image signal corresponding to electrical output of a photosensitive element of the pixel; and an electronic circuit interconnected between said input channel and an output readout utility. The electronic circuit comprises a capacitive unit, and a single analyzer. The capacitive unit is controllably linked to input channel for accumulating charge corresponding to received intensity generated by said pixel during a single frame period, and is connected to output readout utility. The signal analyzer unit is controllably linked to input channel and connected to output readout utility, and is configured for analyzing at least a part of said image signal by determining change in amount of accumulated charge corresponding to the received intensity, and upon detecting that the amount of charge satisfies a predetermined condition generating data indicative of a detected event.

Abstract: A focal plane array detector in a sensor for IR imaging. Pixel readout and analog to digital conversion is performed in an integrated circuit which includes the imaging array. The charge of each pixel is accumulated in a capacitor (16) and a digital to analog charge converter cancels this charge. A controller controls this charge converter providing the appropriate amount of charge. An analog to digital converter incorporating a comparator (92) switches the controller on/off. In some embodiment a programmable device external to the sensor participates in the control of the analog to digital converter. In a typical embodiment of the invention a cycle generator controls the charge output of the digital to analog converter. In a preferred embodiment the analog to digital converters are grouped wherein all such converters group operate simultaneously.

Abstract: A focal plane array detector in a sensor for IR imaging. Pixel readout and analog to digital conversion is performed in an integrated circuit which includes the imaging array. The charge of each pixel is accumulated in a capacitor (16) and a digital to analog charge converter cancels this charge. A controller controls this charge converter providing the appropriate amount of charge. An analog to digital converter incorporating a comparator (92) switches the controller on/off. In some embodiment a programmable device external to the sensor participates in the control of the analog to digital converter. In a typical embodiment of the invention a cycle generator controls the charge output of the digital to analog converter. In a preferred embodiment the analog to digital converters are grouped wherein all such converters group operate simultaneously.

Abstract: A focal plane array detector in a sensor for IR imaging. Pixel readout and analog to digital conversion is performed in an integrated circuit which includes the imaging array. The charge of each pixel is accumulated in a capacitor and a digital to analog charge converter cancels this charge. A controller controls this charge converter providing the appropriate amount of charge. An analog to digital converter incorporating a comparator switches the controller on/off. In some embodiment a programmable device external to the sensor participates in the control of the analog to digital converter. In a typical embodiment of the invention a cycle generator controls the charge output of the digital to analog converter. In a preferred embodiment the analog to digital converters are grouped wherein all such converters group operate simultaneously.