Patents by Inventor Shimon Teshima

Shimon Teshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230283926
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 7, 2023
    Applicant: SONY GROUP CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 11696053
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: July 4, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20230013673
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: September 20, 2022
    Publication date: January 19, 2023
    Applicant: SONY GROUP CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 11483509
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: October 25, 2022
    Assignee: SONY CORPORATION
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20210099660
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 10911707
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: February 2, 2021
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20200236319
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 10659716
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20200007806
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 10432884
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20180270438
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 20, 2018
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 10021335
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 10, 2018
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20170201702
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: May 21, 2015
    Publication date: July 13, 2017
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 9025062
    Abstract: A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first circuit section, a second circuit section, and a stacked structure in which the first and second circuit sections are bonded, wherein the first circuit section has the pixel array unit disposed therein, and wherein the second circuit section has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: May 5, 2015
    Assignee: Sony Corporation
    Inventors: Shimon Teshima, Kenichi Shigenami, Akihiko Miyanohara, Shoji Kobayashi
  • Publication number: 20140253770
    Abstract: A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first circuit section, a second circuit section, and a stacked structure in which the first and second circuit sections are bonded, wherein the first circuit section has the pixel array unit disposed therein, and wherein the second circuit section has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.
    Type: Application
    Filed: May 20, 2014
    Publication date: September 11, 2014
    Applicant: Sony Corporation
    Inventors: Shimon Teshima, Kenichi Shigenami, Akihiko Miyanohara, Shoji Kobayashi
  • Patent number: 8767107
    Abstract: A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first chip, a second chip, and a stacked structure in which both the first chip and the second chip are bonded, wherein the first chip has the pixel array unit disposed therein, and wherein the second chip has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: July 1, 2014
    Assignee: Sony Corporation
    Inventors: Shimon Teshima, Kenichi Shigenami, Akihiko Miyanohara, Shoji Kobayashi