Patents by Inventor Shimpei Tsujikawa
Shimpei Tsujikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240057370Abstract: A light emitting element, display device, and method of manufacture of the same are disclosed. In one example, a light emitting element includes a lower layer/interlayer insulation layer; a light reflection layer formed on the lower layer/interlayer insulation layer; an upper layer/interlayer insulation layer; a first electrode formed on the upper layer/interlayer insulation layer; an insulation film formed at least on a region of the upper layer/interlayer insulation layer where the first electrode is not formed; an organic layer formed over the insulation film from above the first electrode, the organic layer having a light emitting layer including an organic light emitting material; and a second electrode formed on the organic layer. A groove is formed in a portion of the upper layer/interlayer insulation layer located in an edge region of the light emitting element, and an upper portion of the groove is closed with the insulation film.Type: ApplicationFiled: July 7, 2023Publication date: February 15, 2024Inventors: Takayoshi Kato, Naoya Kasahara, Shimpei Tsujikawa
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Patent number: 11765923Abstract: A light emitting element, display device, and method of manufacture of the same are disclosed. In one example, a light emitting element includes a lower layer/interlayer insulation layer; a light reflection layer formed on the lower layer/interlayer insulation layer; an upper layer/interlayer insulation layer; a first electrode formed on the upper layer/interlayer insulation layer; an insulation film formed at least on a region of the upper layer/interlayer insulation layer where the first electrode is not formed; an organic layer formed over the insulation film from above the first electrode, the organic layer having a light emitting layer including an organic light emitting material; and a second electrode formed on the organic layer. A groove is formed in a portion of the upper layer/interlayer insulation layer located in an edge region of the light emitting element, and an upper portion of the groove is closed with the insulation film.Type: GrantFiled: May 6, 2021Date of Patent: September 19, 2023Assignee: Sony Group CorporationInventors: Takayoshi Kato, Naoya Kasahara, Shimpei Tsujikawa
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Publication number: 20220029123Abstract: A light emitting element, display device, and method of manufacture of the same are disclosed. In one example, a light emitting element includes a lower layer/interlayer insulation layer; a light reflection layer formed on the lower layer/interlayer insulation layer; an upper layer/interlayer insulation layer; a first electrode formed on the upper layer/interlayer insulation layer; an insulation film formed at least on a region of the upper layer/interlayer insulation layer where the first electrode is not formed; an organic layer formed over the insulation film from above the first electrode, the organic layer having a light emitting layer including an organic light emitting material; and a second electrode formed on the organic layer. A groove is formed in a portion of the upper layer/interlayer insulation layer located in an edge region of the light emitting element, and an upper portion of the groove is closed with the insulation film.Type: ApplicationFiled: May 6, 2021Publication date: January 27, 2022Inventors: Takayoshi Kato, Naoya Kasahara, Shimpei Tsujikawa
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Patent number: 11100857Abstract: [Object] To provide a display device that displays a display image with high resolution and higher uniformity, and an electronic apparatus including the display device. [Solution] A display device including: a driving transistor including a first-conductivity-type activation region provided in a semiconductor substrate, an opening provided to cross the activation region, a gate insulating film provided on the activation region including an inside of the opening, a gate electrode filling the opening, and second-conductivity-type diffusion regions provided on both sides of the activation region across the opening; and an organic electroluminescent element configured to be driven by the driving transistor.Type: GrantFiled: February 14, 2017Date of Patent: August 24, 2021Assignee: Sony CorporationInventor: Shimpei Tsujikawa
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Patent number: 11024823Abstract: A light emitting element, display device, and method of manufacture of the same are disclosed. In one example, a light emitting element includes a lower layer/interlayer insulation layer; a light reflection layer formed on the lower layer/interlayer insulation layer; an upper layer/interlayer insulation layer; a first electrode formed on the upper layer/interlayer insulation layer; an insulation film formed at least on a region of the upper layer/interlayer insulation layer where the first electrode is not formed; an organic layer formed over the insulation film from above the first electrode, the organic layer having a light emitting layer including an organic light emitting material; and a second electrode formed on the organic layer. A groove is formed in a portion of the upper layer/interlayer insulation layer located in an edge region of the light emitting element, and an upper portion of the groove is closed with the insulation film.Type: GrantFiled: April 29, 2019Date of Patent: June 1, 2021Assignee: Sony CorporationInventors: Takayoshi Kato, Naoya Kasahara, Shimpei Tsujikawa
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Publication number: 20190259972Abstract: A light emitting element, display device, and method of manufacture of the same are disclosed. In one example, a light emitting element includes a lower layer/interlayer insulation layer; a light reflection layer formed on the lower layer/interlayer insulation layer; an upper layer/interlayer insulation layer; a first electrode formed on the upper layer/interlayer insulation layer; an insulation film formed at least on a region of the upper layer/interlayer insulation layer where the first electrode is not formed; an organic layer formed over the insulation film from above the first electrode, the organic layer having a light emitting layer including an organic light emitting material; and a second electrode formed on the organic layer. A groove is formed in a portion of the upper layer/interlayer insulation layer located in an edge region of the light emitting element, and an upper portion of the groove is closed with the insulation film.Type: ApplicationFiled: April 29, 2019Publication date: August 22, 2019Inventors: Takayoshi Kato, Naoya Kasahara, Shimpei Tsujikawa
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Patent number: 10326096Abstract: A light emitting element, display device, and method of manufacture of the same are disclosed. In one example, a light emitting element includes a lower layer/interlayer insulation layer; a light reflection layer formed on the lower layer/interlayer insulation layer; an upper layer/interlayer insulation layer; a first electrode formed on the upper layer/interlayer insulation layer; an insulation film formed at least on a region of the upper layer/interlayer insulation layer where the first electrode is not formed; an organic layer formed over the insulation film from above the first electrode, the organic layer having a light emitting layer including an organic light emitting material; and a second electrode formed on the organic layer. A groove is formed in a portion of the upper layer/interlayer insulation layer located in an edge region of the light emitting element, and an upper portion of the groove is closed with the insulation film.Type: GrantFiled: June 24, 2016Date of Patent: June 18, 2019Assignee: Sony CorporationInventors: Takayoshi Kato, Naoya Kasahara, Shimpei Tsujikawa
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Publication number: 20190139489Abstract: [Object] To provide a display device that displays a display image with high resolution and higher uniformity, and an electronic apparatus including the display device. [Solution] A display device including: a driving transistor including a first-conductivity-type activation region provided in a semiconductor substrate, an opening provided to cross the activation region, a gate insulating film provided on the activation region including an inside of the opening, a gate electrode filling the opening, and second-conductivity-type diffusion regions provided on both sides of the activation region across the opening; and an organic electroluminescent element configured to be driven by the driving transistor.Type: ApplicationFiled: February 14, 2017Publication date: May 9, 2019Inventor: Shimpei Tsujikawa
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Publication number: 20180219170Abstract: A light emitting element, display device, and method of manufacture of the same are disclosed. In one example, a light emitting element includes a lower layer/interlayer insulation layer; a light reflection layer formed on the lower layer/interlayer insulation layer; an upper layer/interlayer insulation layer; a first electrode formed on the upper layer/interlayer insulation layer; an insulation film formed at least on a region of the upper layer/interlayer insulation layer where the first electrode is not formed; an organic layer formed over the insulation film from above the first electrode, the organic layer having a light emitting layer including an organic light emitting material; and a second electrode formed on the organic layer. A groove is formed in a portion of the upper layer/interlayer insulation layer located in an edge region of the light emitting element, and an upper portion of the groove is closed with the insulation film.Type: ApplicationFiled: June 24, 2016Publication date: August 2, 2018Inventors: Takayoshi Kato, Naoya Kasahara, Shimpei Tsujikawa
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Patent number: 9899385Abstract: A semiconductor integrated circuit includes a protected circuit connected to two power supply lines that provide a supply voltage, a detecting circuit that includes a resistive element and a capacitive element connected in series between two power supply lines and detects a surge generated in the power supply line based on potential variation of an inter-element connecting node, and a protection transistor that is connected between two power supply lines and has a control electrode connected to an output of the detecting circuit. The protection transistor has the control electrode formed from a different electrode material having a work function difference from a transistor of the same channel conductivity type in the protected circuit, to have a different threshold voltage from the transistor so that the amount of leakage current per unit channel width may be smaller compared with the transistor.Type: GrantFiled: May 25, 2012Date of Patent: February 20, 2018Assignee: SONY CORPORATIONInventors: Takashi Yamazaki, Shimpei Tsujikawa
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Patent number: 9214496Abstract: A transistor includes: a gate electrode; a semiconductor layer facing the gate electrode with an insulating layer in between; a pair of source-drain electrodes electrically connected to the semiconductor layer; and a contact layer provided in a moving path of carriers between each of the pair of source-drain electrodes and the semiconductor layer, the contact layer having end surfaces covered with the source-drain electrode.Type: GrantFiled: February 2, 2015Date of Patent: December 15, 2015Assignee: Sony CorporationInventors: Shinichi Ushikura, Akihiro Nomoto, Ryouichi Yasuda, Akira Yumoto, Nobuhide Yoneya, Shimpei Tsujikawa
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Publication number: 20150179707Abstract: A transistor includes: a gate electrode; a semiconductor layer facing the gate electrode with an insulating layer in between; a pair of source-drain electrodes electrically connected to the semiconductor layer; and a contact layer provided in a moving path of carriers between each of the pair of source-drain electrodes and the semiconductor layer, the contact layer having end surfaces covered with the source-drain electrode.Type: ApplicationFiled: February 2, 2015Publication date: June 25, 2015Applicant: Sony CorporationInventors: Shinichi Ushikura, Akihiro Nomoto, Ryouichi Yasuda, Akira Yumoto, Nobuhide Yoneya, Shimpei Tsujikawa
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Patent number: 8981375Abstract: A transistor includes: a gate electrode; a semiconductor layer facing the gate electrode with an insulating layer in between; a pair of source-drain electrodes electrically connected to the semiconductor layer; and a contact layer provided in a moving path of carriers between each of the pair of source-drain electrodes and the semiconductor layer, the contact layer having end surfaces covered with the source-drain electrode.Type: GrantFiled: November 16, 2012Date of Patent: March 17, 2015Assignee: Sony CorporationInventors: Shinichi Ushikura, Akihiro Nomoto, Ryouichi Yasuda, Akira Yumoto, Nobuhide Yoneya, Shimpei Tsujikawa
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Publication number: 20120307410Abstract: A semiconductor integrated circuit includes a protected circuit connected to two power supply lines that provide a supply voltage, a detecting circuit that includes a resistive element and a capacitive element connected in series between two power supply lines and detects a surge generated in the power supply line based on potential variation of an inter-element connecting node, and a protection transistor that is connected between two power supply lines and has a control electrode connected to an output of the detecting circuit. The protection transistor has the control electrode formed from a different electrode material having a work function difference from a transistor of the same channel conductivity type in the protected circuit, to have a different threshold voltage from the transistor so that the amount of leakage current per unit channel width may be smaller compared with the transistor.Type: ApplicationFiled: May 25, 2012Publication date: December 6, 2012Applicant: SONY CORPORATIONInventors: Takashi Yamazaki, Shimpei Tsujikawa
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Publication number: 20110031981Abstract: A valuation method of a dielectric breakdown lifetime of a gate insulating film for evaluating the dielectric breakdown lifetime of the gate insulating film of a MOS type element includes the steps of: deciding a Weibull slope of lifetime distribution until reaching a soft breakdown of the gate insulating film of the MOS type element; deciding a detection condition of the soft breakdown from the decided Weibull slope after the above step; and executing a dielectric breakdown test by using the decided detection condition.Type: ApplicationFiled: August 3, 2010Publication date: February 10, 2011Applicant: SONY CORPORATIONInventor: Shimpei Tsujikawa
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Patent number: 7863125Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.Type: GrantFiled: June 26, 2009Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
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Publication number: 20090263945Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.Type: ApplicationFiled: June 26, 2009Publication date: October 22, 2009Applicant: Renesas Technology Corp.,Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
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Patent number: 7569890Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.Type: GrantFiled: April 24, 2006Date of Patent: August 4, 2009Assignee: Renesas Technology Corp.Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
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Patent number: 7432216Abstract: The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm?2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm?2 or more.Type: GrantFiled: August 15, 2006Date of Patent: October 7, 2008Assignee: Hitachi, Ltd.Inventors: Yasuhiro Shimamoto, Shinichi Saito, Shimpei Tsujikawa
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Patent number: 7196384Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogenType: GrantFiled: November 14, 2005Date of Patent: March 27, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Shimpei Tsujikawa, Toshiyuki Mine, Jiro Yugami, Natsuki Yokoyama, Tsuyoshi Yamauchi