Abstract: A coil assembly for wireless electrical power transmission includes a plurality of external connecting terminals, a power feeding coil, a resonant capacitor electrically connecting with the power feeding coil, and busbars each of which electrically connects between the external connecting terminals.

Abstract: An assistance system assisting communication between a supplier providing an article-related service requiring work for an article and a user demanding provision thereof, has: an acquisition unit acquiring three-dimensional model data of the article based on a user instruction; an article presentation unit presenting one of the user and supplier with an article screen expressing the article observed from a predetermined viewpoint, based on the three-dimensional model data; an annotation data generation unit generating annotation data for displaying an annotation screen obtained by writing annotation information on the presented article screen so as to include viewpoint information specifying the viewpoint; an annotation data acquisition unit acquiring the generated annotation data; and an annotation presentation unit presenting another of the user and supplier with the annotation screen based on the acquired annotation data from a viewpoint corresponding to the viewpoint information of the annotation data.

Abstract: A transaction assistance system determining a provision requirement for providing a service, to assist closing a transaction has: a service setting unit setting, in association with service information of each service used in relation to selection of the service, a service candidate group including services providable to the user; an information item setting unit setting, for each service in the service candidate group, an information item necessary for the supplier for determining the provision requirement; a service selection unit selecting the service provided in response to a user demand from the service candidate group using the service information and selection information acquired based on a user instruction; a request acquiring unit acquiring, based on a user instruction, request information for specifying a request by the user for the information item; and a determining unit determining the provision requirement based on the request information.

Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.

Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.

Abstract: A method of manufacturing a semiconductor device includes: forming a first film containing carbon over a silicon nitride film and a first conductive film; forming a first silicon oxide film surrounding the first film over the silicon nitride film and the first conductive film; removing the first film to form, in the first silicon oxide film, a first opening that exposes at least a part of the silicon nitride film and at least a part of the first conductive film; and forming a second conductive film on and in contact with the first conductive film in the first opening.

Abstract: A method including depositing a dielectric film on a substrate including stacked structures with recessed portions formed on side surfaces of each of the stacked structures, wherein the dielectric film is deposited so that the stacked structures are covered at a thickness which is equal to or less than half a width of the recessed portions; filling a trench or trenches that are located between the stacked structures with a sacrificial film; etching the sacrificial film along the stacked structures; etching the dielectric film so that the dielectric film is etched more than the sacrificial film; removing the sacrificial film; after the removing of the sacrificial film, depositing a dielectric film to a thickness equal to or less than half the width of the recessed portions; and etching the deposited dielectric film, on a condition that the deposited dielectric film remains in the recessed portions.

Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.

Abstract: A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.

Abstract: A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.

Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

Abstract: A 4,6-hexadecadiene-2,4-dicarboxylic acid derivative represented by the following general formula (1) or a pharmaceutically acceptable salt thereof, each of which has an anti-tumor activity, and the like, are provided. [wherein, R1 represents hydroxy, —OR3 (wherein R3 represents optionally substituted lower alkyl or an optionally substituted aliphatic heterocyclic group), or —NR4R5 (wherein R4 and R5 may be the same or different, and each represents a hydrogen atom or optionally substituted lower alkyl) and R2 represents hydroxy or —OR6 (wherein R6 represents optionally substituted lower alkyl or optionally substituted aralkyl)].

Abstract: A 4,6-hexadecadiene-2,4-dicarboxylic acid derivative represented by the following general formula (1) or a pharmaceutically acceptable salt thereof, each of which has an anti-tumor activity, and the like, are provided.