Patents by Inventor Shimpei Yamaguchi

Shimpei Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375684
    Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 2, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Shimpei YAMAGUCHI, Atsushi TSUBOI, Atsushi ENDO, Masaru SUGIMOTO, Hiroshi YANO, Yasushi KODASHIMA, Masanobu IGETA
  • Publication number: 20210376123
    Abstract: A method including depositing a dielectric film on a substrate including stacked structures with recessed portions formed on side surfaces of each of the stacked structures, wherein the dielectric film is deposited so that the stacked structures are covered at a thickness which is equal to or less than half a width of the recessed portions; filling a trench or trenches that are located between the stacked structures with a sacrificial film; etching the sacrificial film along the stacked structures; etching the dielectric film so that the dielectric film is etched more than the sacrificial film; removing the sacrificial film; after the removing of the sacrificial film, depositing a dielectric film to a thickness equal to or less than half the width of the recessed portions; and etching the deposited dielectric film, on a condition that the deposited dielectric film remains in the recessed portions.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 2, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Shimpei YAMAGUCHI, Atsushi TSUBOI, Atsushi ENDO, Masanobu IGETA, Masaru SUGIMOTO, Luis FERNANDEZ
  • Patent number: 11056398
    Abstract: A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: July 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Daniel J. Jaeger, Naved A. Siddiqui, Shimpei Yamaguchi, Shreesh Narasimha
  • Publication number: 20210028067
    Abstract: A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Inventors: Daniel J. Jaeger, Naved A. Siddiqui, Shimpei Yamaguchi, Shreesh Narasimha
  • Patent number: 10832966
    Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
  • Publication number: 20190355832
    Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 21, 2019
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Patent number: 10453936
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Publication number: 20190259668
    Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
  • Publication number: 20190131429
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Patent number: 9831098
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xinyuan Dou, Sukwon Hong, Satyajit Shinde, Sandeep Gaan, Tao Han, Carlos Chacon, Shimpei Yamaguchi
  • Publication number: 20170018452
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.
    Type: Application
    Filed: July 13, 2015
    Publication date: January 19, 2017
    Inventors: Xinyuan Dou, Sukwon Hong, Satyajit Shinde, Sandeep Gaan, Tao Han, Carlos Chacon, Shimpei Yamaguchi
  • Patent number: 9260459
    Abstract: A 4,6-hexadecadiene-2,4-dicarboxylic acid derivative represented by the following general formula (1) or a pharmaceutically acceptable salt thereof, each of which has an anti-tumor activity, and the like, are provided. [wherein, R1 represents hydroxy, —OR3 (wherein R3 represents optionally substituted lower alkyl or an optionally substituted aliphatic heterocyclic group), or —NR4R5 (wherein R4 and R5 may be the same or different, and each represents a hydrogen atom or optionally substituted lower alkyl) and R2 represents hydroxy or —OR6 (wherein R6 represents optionally substituted lower alkyl or optionally substituted aralkyl)].
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 16, 2016
    Assignee: Kyowa Hakko Kirin Co., Ltd.
    Inventors: Shimpei Yamaguchi, Yumiko Uochi, Tsutomu Agatsuma, Susumu Iwamoto, Hideyuki Onodera
  • Publication number: 20150183809
    Abstract: A 4,6-hexadecadiene-2,4-dicarboxylic acid derivative represented by the following general formula (1) or a pharmaceutically acceptable salt thereof, each of which has an anti-tumor activity, and the like, are provided.
    Type: Application
    Filed: June 25, 2013
    Publication date: July 2, 2015
    Inventors: Shimpei Yamaguchi, Yumiko Uochi, Tsutomu Agatsuma, Susumu Iwamoto, Hideyuki Onodera