Patents by Inventor Shimpei Yoshioka

Shimpei Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070165383
    Abstract: By providing a plurality of semiconductor chips that are connected in parallel and constitute one arm of an inverter; a first conductor to which a face on one side of said plurality of semiconductor chips is connected; a wide conductor to which a face on the other side of said plurality of semiconductor chips is connected; a second conductor connected to said wide conductor; and a cooler to which said first conductor and second conductor are connected through an insulating resin sheet, part of the heat loss generated in the semiconductor chips is thermally conducted to the first conductor and is thence thermally conducted to the cooler, producing cooling, while another part thereof is thermally conducted to the wide conductor and thence to the second conductor, whence it is thermally conducted to the cooler, producing cooling.
    Type: Application
    Filed: March 22, 2007
    Publication date: July 19, 2007
    Inventors: Toshiharu Obu, Nobumitsu Tada, Hiroki Sekiya, Keizo Hagiwara, Shimpei Yoshioka
  • Patent number: 7206205
    Abstract: By providing a plurality of semiconductor chips that are connected in parallel and constitute one arm of an inverter; a first conductor to which a face on one side of said plurality of semiconductor chips is connected; a wide conductor to which a face on the other side of said plurality of semiconductor chips is connected; a second conductor connected to said wide conductor; and a cooler to which said first conductor and second conductor are connected through an insulating resin sheet, part of the heat loss generated in the semiconductor chips is thermally conducted to the first conductor and is thence thermally conducted to the cooler, producing cooling, while another part thereof is thermally conducted to the wide conductor and thence to the second conductor, whence it is thermally conducted to the cooler, producing cooling.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: April 17, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiharu Obu, Nobumitsu Tada, Hiroki Sekiya, Keizo Hagiwara, Shimpei Yoshioka
  • Publication number: 20060164813
    Abstract: A semiconductor package includes a plate-like semiconductor element having a first power terminal and a control terminal on a main surface, and a second power terminal on a rear surface; a first power electrode plate positioned to face with the main surface of the semiconductor element, and including a first power electrode joined to the first power terminal by soldering; a second power electrode plate positioned to face with the rear surface of the semiconductor element, and including a second power electrode joined to the second power terminal by soldering; and an insulating substrate positioned between the semiconductor element and the first electrode plate, and including a control electrode joined to the control terminal by soldering.
    Type: Application
    Filed: November 30, 2005
    Publication date: July 27, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shimpei Yoshioka, Yukihiro Ikeya, Naotake Watanabe, Nobumitsu Tada, Masakazu Shindome
  • Publication number: 20050057901
    Abstract: By providing a plurality of semiconductor chips that are connected in parallel and constitute one arm of an inverter; a first conductor to which a face on one side of said plurality of semiconductor chips is connected; a wide conductor to which a face on the other side of said plurality of semiconductor chips is connected; a second conductor connected to said wide conductor; and a cooler to which said first conductor and second conductor are connected through an insulating resin sheet, part of the heat loss generated in the semiconductor chips is thermally conducted to the first conductor and is thence thermally conducted to the cooler, producing cooling, while another part thereof is thermally conducted to the wide conductor and thence to the second conductor, whence it is thermally conducted to the cooler, producing cooling.
    Type: Application
    Filed: March 31, 2004
    Publication date: March 17, 2005
    Inventors: Toshiharu Obu, Nobumitsu Tada, Hiroki Sekiya, Keizo Hagiwara, Shimpei Yoshioka
  • Patent number: 6255672
    Abstract: A semiconductor device includes a pair of semiconductor switching elements and a board. Each semiconductor switching element has positive and control electrodes formed on one surface and a negative electrode formed on the other surface. The positive and control electrodes of one of the semiconductor switching elements are joined to the board, and the negative electrode of the other semiconductor switching element, which faces in a direction opposite to that of one of the semiconductor switching elements, is joined to the board.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: July 3, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shimpei Yoshioka, Yasuhito Saito
  • Patent number: 6161195
    Abstract: This invention provides a memory card device using an EEPROM as a semiconductor memory. When a data write-in defective area is detected in the storage area of the EEPROM, a space area is retrieved from the storage area of the EEPROM as a relieving area and data to be written into the data write-in defective area is written into the relieving area. Then, when the relieving area becomes full and a data write-in defective area is detected in the storage area of the EEPROM, another space area is retrieved from the storage area of the EEPROM as a new relieving area and data to be written into the data write-in defective area is written into the new relieving area.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: December 12, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Konishi, Shimpei Yoshioka, Koji Maruyama, Tomoyuki Maekawa, Toshiaki Sato
  • Patent number: 5808878
    Abstract: A circuit substrate which is formed by fixing a wiring pattern on an insulated substrate has a shielding member for absorbing or reflecting radio waves formed on a first electronic component electrically connected. A shielding layer for absorbing or reflecting radio waves is formed on the circuit substrate. And, a second electronic component is disposed between the first electronic component and the shielding layer.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: September 15, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhito Saito, Youko Maekawa, Shimpei Yoshioka
  • Patent number: 5745912
    Abstract: A memory card apparatus has an EEPROM as a semiconductor memory. Each time data is written in the EEPROM, link data representing a recording location of the data is written and managed in a link table. The link table has a flag region with a flag which is set when data write in the EEPROM is requested and is reset when the link data has completely been written in the link table. In case of card removal during operation or power failure, the flag set in the flag region of the link table is not reset and remains. Thus, by checking the flag area of the link table, the occurrence of card removal during operation or power failure can be detected, and various countermeasures can be conducted. Thus, the correspondency between the recorded contents in the EEPROM and the contents in the link table can be maintained as much as possible.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: April 28, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Konishi, Shimpei Yoshioka, Koji Maruyama, Tomoyuki Maekawa, Toshiaki Sato
  • Patent number: 5579502
    Abstract: A memory card apparatus using EEPROMs as semiconductor memories. Externally input data are temporarily recorded in a buffer memory and are subsequently written in the EEPROMs. Verify processing is automatically performed between the buffer memory and the EEPROMs. Similarly, data read out from the EEPROMs are temporarily recorded in the buffer memory and are subsequently output to an external unit. Even with the EEPROMs, it seems that this memory card can be used in the same manner as a memory card using an SRAM, when viewed from the outside of the card.
    Type: Grant
    Filed: July 21, 1995
    Date of Patent: November 26, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Konishi, Shimpei Yoshioka, Setsuo Terasaki, Hiroaki Matsubara, Koji Maruyama, Toshiaki Sato, Takaaki Suyama
  • Patent number: 5483491
    Abstract: The present invention relates to a memory card apparatus. When one of blocks of a data area of an EEPROM is detected as a defective block, a save area is searched for a vacant block, and data, which is to be written to the defective block, is written to the vacant block of the data area. When the save area is occupied and one of blocks of the data area is detected as a defective block, the data area is searched for a vacant block, and data, which is to be written to the defective block, is written to the vacant block of the data area. When a block of the data area is used for saving the defective block and a vacant block is generated in the save area by erasing data, data of the block of the data area used for saving the defective block is transferred to the vacant block.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: January 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shimpei Yoshioka, Kazuo Konishi, Koji Maruyama, Toshiaki Sato