Abstract: An integrated circuit (IC) with conductive structures and a method of fabricating the IC are disclosed. The method includes depositing a first dielectric layer on a semiconductor device, forming a conductive structure in the first dielectric layer, removing a portion of the first dielectric layer to expose a sidewall of the conductive structure, forming a barrier structure surrounding the sidewall of the conductive structure, depositing a conductive layer on the barrier structure, and performing a polishing process on the barrier structure and the conductive layer.

Abstract: A method includes forming a fin protruding from a substrate, the fin including an epitaxial stack over a fin base and a hard mask layer over the epitaxial stack, the epitaxial stack including first and second semiconductor layers of different material compositions, performing a first etching process to etch the hard mask layer, the first etching process including applying a first combination of etchants, performing a second etching process to etch the epitaxial stack, the second etching process including applying a second combination of etchants, and performing a third etching process to etch the fin base, the third etching process including applying a third combination of etchants. The first, second, and third combinations of etchants are different from each other.

Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: The present invention discloses a wireless communication apparatus having transmission strategy adjusting mechanism that includes a receiving circuit, a detection circuit, a statistics circuit, a strategy determining circuit and a transmission circuit. The receiving circuit receives communication behaviors of external apparatuses. The detection circuit detects inter frame spaces (IFS) corresponding to the communication behaviors and records related time lengths and a set of communication parameters. The statistics circuit performs statistics on the inter frame space according to a plurality of time intervals to generate Inter frame space statistics data. The strategy determining circuit analyzes at least one of the time lengths, communication parameters and Inter frame space statistics data according to at least one application requirement to generate a transmission parameter adjusting signal.

Abstract: A sensing cell includes: a first electrode coupled to a gate of a transistor, a second electrode spaced apart from the first electrode; a protective layer covering sidewalls of the first electrode and the second electrode and having a first opening and a second opening exposing a first part of the first electrode and a second part of the second electrode, respectively; a first well located on the protective layer and surrounding the first electrode and the second electrode and having a third opening exposing the first part of the first electrode, the second part of the second electrode, and the protective layer between the first opening and the second opening; a second well located on the protective layer surrounding the first well and having a fourth opening to limit a flow of a liquid to be tested; and an ion selective membrane located in the third opening.

Abstract: A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

Abstract: A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.

Abstract: A system may provision a smart device to allow the smart device to communicate using a network and use at least one service of a management platform. A device identifier of the smart device may be stored in a data store accessible to the management platform. The smart device may send a message to the management platform that includes the device identifier, and in some implementations other information such as location information. The management platform may determine that the smart device has been provisioned, for example based on the device identifier or other information, and provide a service to the smart device from the management platform.

Abstract: A sensing cell includes: a first electrode coupled to a gate of a transistor, a second electrode spaced apart from the first electrode; a protective layer covering sidewalls of the first electrode and the second electrode and having a first opening and a second opening exposing a first part of the first electrode and a second part of the second electrode, respectively; a first well located on the protective layer and surrounding the first electrode and the second electrode and having a third opening exposing the first part of the first electrode, the second part of the second electrode, and the protective layer between the first opening and the second opening; a second well located on the protective layer surrounding the first well and having a fourth opening to limit a flow of a liquid to be tested; and an ion selective membrane located in the third opening.

Abstract: A system may provision a smart device to allow the smart device to communicate using a network and use at least one service of a management platform. A device identifier of the smart device may be stored in a data store accessible to the management platform. The smart device may send a message to the management platform that includes the device identifier, and in some implementations other information such as location information. The management platform may determine that the smart device has been provisioned, for example based on the device identifier or other information, and provide a service to the smart device from the management platform.

Abstract: The present disclosure discloses a wall mount device adapted to be fixed to a wall surface and carry an electronic device with connecting wires. The wall mount device comprises a wall mount, a first and a second wire arrangement component. The wall mount has an upper and a lower surface. The upper surface faces the wall surface and the lower surface faces the electronic device. The first wire arrangement component is positioned on the lower surface and adjacent to a first side of the wall mount. The second wire arrangement component is positioned on the lower surface and adjacent to a second side vertical to the first side of the wall mount. The connecting wires are sequentially and detachably accommodated in the first and the second wire arrangement component from the electronic device to fix the connecting wires to corresponding positions on the wall mount.

Abstract: The present disclosure provides for a method of designing a radiofrequency or broadband pulse sequence. The method can comprise a qubit (e.g., nuclear spin, photon, electron, atomic spin, dot spin) and a harmonic oscillator wherein a flip angle is controlled by steering a spring between specific states.

Abstract: A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

Abstract: A detecting method for blood is provided. The method includes the following steps. A sensing device including a base and at least one response electrode is provided, wherein the response electrode is spaced apart from a gate end of the base. Blood including blood cells and targets is disposed on the response electrode. The blood is separated into a first part and a second part, wherein the first part is in contact with the response electrode, and the blood cell count in the first part is less than that in the second part. A voltage is applied on the response electrode, such that an electric field is generated between the response electrode and the gate end of the base, and a detection current generated from the base is measured to detect a characterize of the targets.

Abstract: A system for entraining an oscillator ensemble is disclosed that includes a plurality of oscillators in an entrained phase pattern. The system includes an entrainment device operatively coupled to each non-linear oscillator of the oscillator ensemble, and the entrainment control device is configured to deliver a 2?-periodic control signal v(?) to all oscillators of the plurality of oscillators to induce the entrained phase pattern.

Abstract: The present disclosure discloses a wall mount device adapted to be fixed to a wall surface and carry an electronic device with connecting wires. The wall mount device comprises a wall mount, a first and a second wire arrangement component. The wall mount has an upper and a lower surface. The upper surface faces the wall surface and the lower surface faces the electronic device. The first wire arrangement component is positioned on the lower surface and adjacent to a first side of the wall mount. The second wire arrangement component is positioned on the lower surface and adjacent to a second side vertical to the first side of the wall mount. The connecting wires are sequentially and detachably accommodated in the first and the second wire arrangement component from the electronic device to fix the connecting wires to corresponding positions on the wall mount.

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

Abstract: A detecting method for blood is provided. The method includes the following steps. A sensing device including a base and at least one response electrode is provided, wherein the response electrode is spaced apart from a gate end of the base. Blood including blood cells and targets is disposed on the response electrode. The blood is separated into a first part and a second part, wherein the first part is in contact with the response electrode, and the blood cell count in the first part is less than that in the second part. A voltage is applied on the response electrode, such that an electric field is generated between the response electrode and the gate end of the base, and a detection current generated from the base is measured to detect a characterize of the targets.

Abstract: The present disclosure provides for a method of designing a radiofrequency or broadband pulse sequence. The method can comprise a qubit (e.g., nuclear spin, photon, electron, atomic spin, dot spin) and a harmonic oscillator wherein a flip angle is controlled by steering a spring between specific states.

Abstract: A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.