Patents by Inventor Shin Chen Lin

Shin Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12382686
    Abstract: High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: August 5, 2025
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin Lin, Shin-Chen Lin, Yu-Hao Ho, Cheng-Tsung Wu, Chiu-Hao Chen
  • Publication number: 20240413236
    Abstract: A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 12, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yang Du, Shin-chen Lin, Chia-ching Huang
  • Patent number: 12034071
    Abstract: A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: July 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yang Du, Shin-Chen Lin, Chia-Ching Huang
  • Publication number: 20220320289
    Abstract: High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 6, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin Lin, Shin-Chen Lin, Yu-Hao Ho, Cheng-Tsung Wu, Chiu-Hao Chen
  • Publication number: 20220293779
    Abstract: A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 15, 2022
    Inventors: Yang Du, Shin-Chen Lin, Chia-Ching Huang
  • Patent number: 11398552
    Abstract: High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: July 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin Lin, Shin-Chen Lin, Yu-Hao Ho, Cheng-Tsung Wu, Chiu-Hao Chen
  • Publication number: 20220069081
    Abstract: High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 3, 2022
    Inventors: Wen-Hsin Lin, Shin-Chen Lin, Yu-Hao Ho, Cheng-Tsung Wu, Chiu-Hao Chen
  • Publication number: 20020068425
    Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bumps. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.
    Type: Application
    Filed: December 1, 2000
    Publication date: June 6, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yen-Ming Chen, Kuo-Wei Lin, Cheng-Yu Chu, Fu-Jier Fan, Yang-Tung Fan, Chiou-Shian Peng, Shin Chen Lin