Patents by Inventor Shin-Chii Lu

Shin-Chii Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7741169
    Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: June 22, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Shin-Chii Lu, Yu-Ming Lin, Min-Hung Lee, Zing-Way Pei, Wen Yi Hsieh
  • Publication number: 20080311713
    Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.
    Type: Application
    Filed: August 4, 2008
    Publication date: December 18, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shin-Chii Lu, Yu-Ming Lin, Min-Hung Lee, Zing-Way Pei, Wen-Yi Hsieh
  • Publication number: 20070069298
    Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.
    Type: Application
    Filed: December 29, 2005
    Publication date: March 29, 2007
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shin-Chii Lu, Yu-Ming Lin, Min-Hung Lee, Zing-Way Pei, Wen Hsieh
  • Publication number: 20040087097
    Abstract: A manufacture method of a semiconductor device, and more particularly to the manufacture method of a silicon/silicon-germanium heterogeneous bipolar transistor (HBT) device with ultra-thin base, which mainly utilized the method of doping carbon atoms in the silicon-germanium (SiGe) spacer layer in order to suppress the out-diffusion of boron, increase the amount of doped boron in base, germanium (Ge) concentration, and critical thickness, and decrease the thickness of silicon-germanium spacer layer, and achieve the objective of raising the device's high frequency property.
    Type: Application
    Filed: April 28, 2003
    Publication date: May 6, 2004
    Applicant: Industrial Technology Research Institute
    Inventors: Li-Shyue Lai, Pang-Shiu Chen, Shin-Chii Lu, Chee-Wee Liu
  • Publication number: 20030219963
    Abstract: Within an epitaxial base bipolar transistor device and a method for fabricating the epitaxial base bipolar transistor device there is provided: (1) a monocrystalline semiconductor substrate which serves as a collector, in turn having formed thereupon; (2) an epitaxial base layer. Within the epitaxial base bipolar transistor device and method, there is further employed: (1) a pair of inward facing spacers formed over the epitaxial base layer and defining, at least in part, an aperture having at its bottom a portion of the epitaxial base layer; and (2) a pair of outward facing spacers formed over the epitaxial base layer and laminated to a pair of sides of the pair of inward facing spacers opposite the aperture; such that (3) an emitter layer may be formed into the aperture and contacting the epitaxial base layer. The foregoing two pair of spacer layers provide for efficient fabrication of the epitaxial base bipolar transistor device, with enhanced process latitude.
    Type: Application
    Filed: May 23, 2002
    Publication date: November 27, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Hung Shen, Shin-Chii Lu, Lurng-Shehng Lee
  • Patent number: 6046109
    Abstract: The present invention solves the problem of how to form local regions of semi-insulating material within a single crystal substrate. It does this by irradiating the semiconductor with a high energy beam capable of producing radiation damage along its path. As a consequence of such radiation damage the resistivity of the semiconductor in the irradiated area is increased by several orders of magnitude, causing it to become semi-insulating. Semi-insulating regions of this type are effective as electrically isolating regions and can be used, for example, to decouple analog from digital circuits or to maintain high Q in integrated inductors after these devices have been made. The radiation used could be electromagnetic (such as X-rays or gamma rays) or it could comprise energetic particles such as protons, deuterons, etc. Confinement of the beam to local regions within the semiconductor is accomplished by means of suitable masks.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: April 4, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Chungpin Liao, Denny D. Tang, Shin-Chii Lu