Abstract: A clock control circuit prevents glitches when turning a clock signal back on after being turned off following a period of system inactivity and includes a first flip-flop, a second flip-flop, and a NAND gate. The first flip-flop receives a direct input beginclk signal and a clock-triggered stopclk signal. The first flip-flop also has an output Q.sub.1. A change in the beginclk signal is indicative of the start of a clock signal. The periodic signal is for triggering the storage of the stopclk signal in the first flip-flop. The second flip-flop receives the direct input beginclk signal and the output Q.sub.1 of the first flip-flop as a clock-triggered input. The second flip-flop also has an output Q.sub.2. The periodic signal is also for triggering the storage of the output Q.sub.1 of the first storage element in the second storage element. The NAND gate receives the output Q.sub.2 of the second flip-flop as a first input. The output Q.sub.