Abstract: Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be to adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern.

Abstract: Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern.

Abstract: Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern.