Abstract: A resource sharing method for a resource sharing system for a plurality of edge peers that individually store a resource and a plurality of super peers that manage the plurality of edge peers or resource information including a name of the resource that includes at least one key word is provided. In the resource sharing system, the super peers distribute and manage resource information of the edge peers according to a key word. Therefore, if a resource is requested using part of a name of a resource desired by a certain edge peer, the super peer searches for resources including the resource desired by the edge peer. Therefore, a user of an edge peer may acquire a desired resource even using part of a name of a desired resource.

Abstract: An image search method may include: determining a quadrant of a predicted motion vector; calculating a tilt value of a first reference frame and a tilt value of a second reference frame using the predicted motion vector; deciding a search area for uneven hexagon search in response to the quadrant of the predicted motion vector and the calculated tilt values; performing the uneven hexagon search with respect to the decided search area; and/or comparing a result of the performed uneven hexagon search with a threshold value to determine termination of the uneven hexagon search. The second reference frame is earlier-in-time relative to the first reference frame.

Abstract: A peer-to-peer (P2P) network system and a method of operating the P2P network system based on region are provided. If an edge peer storing a resource information list of a super peer migrates to a different super peer and is registered and connected with the different super peer, the edge peer transfers the resource information list to the different super peer to share the resource information list. Resources may be searched based on a region information list into which resource information lists of adjacent super peers are integrated.

Abstract: A peer-to-peer (P2P) network system and a method of operating the P2P network system are provided. The P2P network system includes at least one edge peer storing resources and at least one super peer sharing and managing resource information corresponding to the resources of the at least one edge peer. By updating changes in characteristics of peers due to elimination and movement of any one of a plurality of edge peers and super peers included in the P2P network, path reconfiguration may be performed efficiently.

Abstract: A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data according to an input instruction and pipelining the instruction at each cycle for executing a program. The control unit inputs a new instruction to a first PE of the PE array at each cycle.

Abstract: A file-based Message Passing Interface (MPI) job allocation apparatus for a middleware-based grid computing apparatus in which computers having a plurality of computing resources including an MPI program are distributed and connected to each other through a network, includes: a plurality of computational nodes each having a job execution service module for executing a job for the plurality of computing resources including the MPI program included in the distributed computers; and a middleware having a job submission service module for distributing a job to the plurality of computational nodes, receiving information necessary for MPI initialization, generating a file including the information, and transmitting the file to the MPI program.

Abstract: A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data according to an input instruction and pipelining the instruction at each cycle for executing a program. The control unit inputs a new instruction to a first PE of the PE array at each cycle.

Abstract: A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data interconnection unit is configured to shift the plurality of data output from the memory and provide the shifted data to a plurality of operation units as input data. The operation result from each of the plurality of operation units is stored in a region of the memory.

Abstract: A peer-to-peer (P2P) network system and a method of operating the P2P network system based on region are provided. If an edge peer storing a resource information list of a super peer migrates to a different super peer and is registered and connected with the different super peer, the edge peer transfers the resource information list to the different super peer to share the resource information list. Resources may be searched based on a region information list into which resource information lists of adjacent super peers are integrated.

Abstract: A peer-to-peer (P2P) network system and a method of operating the P2P network system are provided. The P2P network system includes at least one edge peer storing resources and at least one super peer sharing and managing resource information corresponding to the resources of the at least one edge peer. By updating changes in characteristics of peers due to elimination and movement of any one of a plurality of edge peers and super peers included in the P2P network, path reconfiguration may be performed efficiently.

Abstract: A resource sharing method for a resource sharing system for a plurality of edge peers that individually store a resource and a plurality of super peers that manage the plurality of edge peers or resource information including a name of the resource that includes at least one key word is provided. In the resource sharing system, the super peers distribute and manage resource information of the edge peers according to a key word. Therefore, if a resource is requested using part of a name of a resource desired by a certain edge peer, the super peer searches for resources including the resource desired by the edge peer. Therefore, a user of an edge peer may acquire a desired resource even using part of a name of a desired resource.

Abstract: A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder (codec).

Abstract: An image search method may include: determining a quadrant of a predicted motion vector; calculating a tilt value of a first reference frame and a tilt value of a second reference frame using the predicted motion vector; deciding a search area for uneven hexagon search in response to the quadrant of the predicted motion vector and the calculated tilt values; performing the uneven hexagon search with respect to the decided search area; and/or comparing a result of the performed uneven hexagon search with a threshold value to determine termination of the uneven hexagon search. The second reference frame is earlier-in-time relative to the first reference frame.

Abstract: A method is provided for controlling a cache system. The cache system to be controlled comprises a direct-mapped cache configured with a small block size, and a fully associative spatial buffer configured with a large block, which includes a plurality of small blocks. Where accesses to the direct-mapped cache and the fully associative buffer are misses, data of a missed address and data of adjacent addresses are copied to the large block in the fully associative spatial buffer according to a first-in-first-out (FIFO) process. Furthermore, if one or more small data blocks is accessed among its corresponding large block of data which is to be expelled from the fully associative buffer, the small block(s) accessed is copied to the direct-mapped cache.

Abstract: A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

Abstract: A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

Abstract: A cache system and a control method therefor are provided. The cache system is organized as a direct-mapped cache configured with a small block size and a fully associative spatial buffer configured with a large block size, consisting of a plurality of small blocks. Here, if accesses to the direct-mapped cache and the fully associative buffer are a miss, data of the accessed address and data of the adjacent addresses are copied to the large block in the fully associative spatial buffer according to a first-in-first-out (FIFO) algorithm. Furthermore, if one or more small data blocks accessed before exist among its corresponding large block of data to be expelled from the fully associative buffer, the small block(s) accessed is copied to the direct-mapped cache.

Abstract: A cache memory system reduces the rate of cache misses. The cache memory system includes a first auxiliary storage device which stores first information blocks and a second auxiliary storage device which stores second information blocks fetched from a lower level memory device. Each second block includes a plurality of the first information blocks. A process for fetching information selectively fetches a first or second information block from the lower level memory device and selectively stores the fetched block in the first auxiliary storage device and/or the second auxiliary storage device. Selection of the size of block to fetch and where to store the fetched block is according to whether the data to be referenced by the central controller is in the first auxiliary storage device or the second auxiliary storage device and whether first information blocks that do not include the referenced data are both in the second information block including the referenced data and in the first auxiliary storage device.

Abstract: A method of and a circuit for instruction/data prefetching using a non-referenced prefetch cache, adapted to store instruction/data blocks prefetched in accordance with a variety of existing prefetchinig machanisms, but not referenced by the central processing unit in an on-chip memory as the non-referenced prefetch cache without discarding them when they are replaced by new ones in a prefetch buffer so that a direct memory reference to the non-referenced prefetch instruction/data blocks can be achieved when they are to be referenced at later times, without any requirement of fetching or prefetching them from the lower memory again. Accordingly, it is possible to not only decrease the number of cache misses and the memory latency due to the fetching of instructions/data from the lower memory for the reference to the instructions/data, but also to reduce memory traffic.

Abstract: A method for storing parity and rebuilding the data contents of two failed disks in an external storage subsystem comprises the steps of: proving a disk array defined as a matrix of (N-1).sup.