Patents by Inventor Shin Gyu Choi

Shin Gyu Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8933509
    Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: January 13, 2015
    Assignee: SK hynix Inc.
    Inventors: Shin Gyu Choi, Seung Chul Oh
  • Publication number: 20130320438
    Abstract: A semiconductor device comprises a gate electrode buried in a trench within a semiconductor substrate, a first sealing insulating film disposed over the gate electrode and the semiconductor substrate, an ion-implanting region disposed in portions of the semiconductor substrate adjacent to sidewalls of the trench, and a second sealing insulating film formed over the first sealing insulating film to bury the trench.
    Type: Application
    Filed: October 11, 2012
    Publication date: December 5, 2013
    Applicant: SK HYNIX INC.
    Inventor: Shin Gyu CHOI
  • Publication number: 20110121388
    Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.
    Type: Application
    Filed: February 8, 2011
    Publication date: May 26, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Shin Gyu CHOI, Seung Chul OH
  • Patent number: 7892944
    Abstract: A method of forming a transistor in a semiconductor device includes forming device isolation structures in a substrate to define an active region. An oxide-based layer and a nitride-based layer are then formed between the active region and the device isolation structures. A predetermined gate region is etched in the active region to form a recess region. The damage layers are formed by a tilted ion implantation process using neutral elements on portions of the oxide-based layer exposed at the sidewalls of the recess region and other portions of the oxide-based layer below the recess region. The damage layers are then removed, thus causing a portion of the active region exposed at the bottom of the recess region to protrude.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: February 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Shin-Gyu Choi
  • Patent number: 7883965
    Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, and a gate electrode. The device isolation structure is formed in a semiconductor substrate to define an active region. The recess channel structure is disposed in the semiconductor substrate under the active region. The gate electrode includes a holding layer disposed in a gate region to fill the recess channel structure. The holding layer prevents a seam and a shift of the seam occurring in the recess channel structure.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: February 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Shin Gyu Choi, Seung Chul Oh
  • Publication number: 20100129979
    Abstract: The disclosed semiconductor device includes a plurality of active patterns including first active patterns which protrude from a semiconductor substrate and have a first width and second active patterns which are connected to upper ends of the respective first active patterns and have a second width greater than the first width. The semiconductor device further includes isolation patterns respectively located between the active patterns to insulate the active patterns from one another.
    Type: Application
    Filed: January 28, 2010
    Publication date: May 27, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Shin Gyu CHOI
  • Publication number: 20100055866
    Abstract: A method of forming a transistor in a semiconductor device includes forming device isolation structures in a substrate to define an active region. An oxide-based layer and a nitride-based layer are then formed between the active region and the device isolation structures. A predetermined gate region is etched in the active region to form a recess region. The damage layers are formed by a tilted ion implantation process using neutral elements on portions of the oxide-based layer exposed at the sidewalls of the recess region and other portions of the oxide-based layer below the recess region. The damage layers are then removed, thus causing a portion of the active region exposed at the bottom of the recess region to protrude.
    Type: Application
    Filed: December 26, 2008
    Publication date: March 4, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Shin-Gyu CHOI
  • Publication number: 20090108395
    Abstract: The disclosed semiconductor device includes a plurality of active patterns including first active patterns which protrude from a semiconductor substrate and have a first width and second active patterns which are connected to upper ends of the respective first active patterns and have a second width greater than the first width. The semiconductor device further includes isolation patterns respectively located between the active patterns to insulate the active patterns from one another.
    Type: Application
    Filed: May 9, 2008
    Publication date: April 30, 2009
    Inventor: Shin Gyu CHOI
  • Publication number: 20080023753
    Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, and a gate electrode. The device isolation structure is formed in a semiconductor substrate to define an active region. The recess channel structure is disposed in the semiconductor substrate under the active region. The gate electrode includes a holding layer disposed in a gate region to fill the recess channel structure. The holding layer prevents a seam and a shift of the seam occurring in the recess channel structure.
    Type: Application
    Filed: December 30, 2006
    Publication date: January 31, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Shin Gyu Choi, Seung Chul Oh