Patents by Inventor Shin-Hao LIU

Shin-Hao LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10147636
    Abstract: A method for fabricating a trench isolation structure is provided. The method includes providing a substrate and forming a patterned mask layer on the substrate. A first etching step is performed on the substrate by using the patterned mask layer to form a trench in the substrate. A dielectric material is formed in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height. An etch back step is performed to decrease the dielectric material on the patterned mask layer to a second height. A planarization process is performed to remove the dielectric material on the patterned mask layer, where a polishing pad is used, and a first pressure and a second pressure are respectively applied on a central portion and a peripheral portion of the polishing pad, wherein the second pressure is greater than the first pressure.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 4, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shin-Hao Liu, Chih-Cherng Liao, Ching-Yi Hsu, Yun-Chou Wei
  • Publication number: 20170372944
    Abstract: A method for fabricating a trench isolation structure is provided. The method includes providing a substrate and forming a patterned mask layer on the substrate. A first etching step is performed on the substrate by using the patterned mask layer to form a trench in the substrate. A dielectric material is formed in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height. An etch back step is performed to decrease the dielectric material on the patterned mask layer to a second height. A planarization process is performed to remove the dielectric material on the patterned mask layer, where a polishing pad is used, and a first pressure and a second pressure are respectively applied on a central portion and a peripheral portion of the polishing pad, wherein the second pressure is greater than the first pressure.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shin-Hao LIU, Chih-Cherng LIAO, Ching-Yi HSU, Yun-Chou WEI