Patents by Inventor Shin Hirotsu
Shin Hirotsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006154Abstract: A plasma processing method according to an exemplary embodiment includes applying a first direct-current voltage to a lower electrode of a substrate support provided in a chamber of a plasma processing apparatus, in a first period during generation of plasma in the chamber. The plasma processing method further includes applying a second direct-current voltage to the lower electrode in a second period different from the first period during generation of plasma in the chamber. The second direct-current voltage has a level different from a level of the first direct-current voltage. The second direct-current voltage has a same polarity as a polarity of the first direct-current voltage.Type: ApplicationFiled: August 10, 2023Publication date: January 4, 2024Applicant: Tokyo Electron LimitedInventors: Chishio KOSHIMIZU, Shin HIROTSU, Takenobu IKEDA, Koichi NAGAMI, Shinji HIMORI
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Patent number: 11830704Abstract: A plasma processing apparatus includes: a processing container; an electrode that places a workpiece thereon; a plasma generation source that supplies plasma into the processing container; a bias power supply that supplies a bias power to the electrode; an edge ring disposed at a periphery of the workpiece; a DC power supply that supplies a DC voltage to the edge ring; a controller that executes a first control procedure in which the DC voltage periodically repeats a first state having a first voltage value and a second state having a second voltage value, the first voltage value is supplied in a partial time period within each period of a potential of the electrode, and the second voltage value is supplied such that the first and second states are continuous.Type: GrantFiled: January 25, 2023Date of Patent: November 28, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Chishio Koshimizu, Shin Hirotsu
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Patent number: 11764034Abstract: A plasma processing method according to an exemplary embodiment includes applying a first direct-current voltage to a lower electrode of a substrate support provided in a chamber of a plasma processing apparatus, in a first period during generation of plasma in the chamber. The plasma processing method further includes applying a second direct-current voltage to the lower electrode in a second period different from the first period during generation of plasma in the chamber. The second direct-current voltage has a level different from a level of the first direct-current voltage. The second direct-current voltage has a same polarity as a polarity of the first direct-current voltage.Type: GrantFiled: May 19, 2020Date of Patent: September 19, 2023Assignee: Tokyo Electron LimitedInventors: Chishio Koshimizu, Shin Hirotsu, Takenobu Ikeda, Koichi Nagami, Shinji Himori
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Patent number: 11574798Abstract: A plasma processing apparatus includes a container; a stage disposed in the container and including an electrode; a plasma source that generates plasma in the container; a bias power supply that periodically supplies a pulsed negative DC voltage to the electrode; an edge ring disposed to surround a substrate placed on the stage; and a DC power supply that supplies a DC voltage to the edge ring. The DC power supply supplies a first DC voltage in a first time period when the pulsed negative DC voltage is not supplied to the electrode, and supplies a second DC voltage in a second time period when the pulsed negative DC voltage is supplied to the electrode.Type: GrantFiled: May 12, 2020Date of Patent: February 7, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Chishio Koshimizu, Shin Hirotsu
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Publication number: 20200381215Abstract: A plasma processing method according to an exemplary embodiment includes applying a first direct-current voltage to a lower electrode of a substrate support provided in a chamber of a plasma processing apparatus, in a first period during generation of plasma in the chamber. The plasma processing method further includes applying a second direct-current voltage to the lower electrode in a second period different from the first period during generation of plasma in the chamber. The second direct-current voltage has a level different from a level of the first direct-current voltage. The second direct-current voltage has a same polarity as a polarity of the first direct-current voltage.Type: ApplicationFiled: May 19, 2020Publication date: December 3, 2020Applicant: Tokyo Electron LimitedInventors: Chishio KOSHIMIZU, Shin HIROTSU, Takenobu IKEDA, Koichi NAGAMI, Shinji HIMORI
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Publication number: 20200273670Abstract: A plasma processing apparatus includes: a processing container; an electrode that places a workpiece thereon; a plasma generation source that supplies plasma into the processing container; a bias power supply that supplies a bias power to the electrode; an edge ring disposed at a periphery of the workpiece; a DC power supply that supplies a DC voltage to the edge ring; a controller that executes a first control procedure in which the DC voltage periodically repeats a first state having a first voltage value and a second state having a second voltage value, the first voltage value is supplied in a partial time period within each period of a potential of the electrode, and the second voltage value is supplied such that the first and second states are continuous.Type: ApplicationFiled: May 12, 2020Publication date: August 27, 2020Applicant: TOKYO ELECTRON LIMITEDInventors: Chishio KOSHIMIZU, Shin HIROTSU
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Patent number: 10672589Abstract: A plasma processing apparatus includes: a processing container; an electrode that places a workpiece thereon; a plasma generation source that supplies plasma into the processing container; a bias power supply that supplies a bias power to the electrode; an edge ring disposed at a periphery of the workpiece; a DC power supply that supplies a DC voltage to the edge ring; a controller that executes a first control procedure in which the DC voltage periodically repeats a first state having a first voltage value and a second state having a second voltage value, the first voltage value is supplied in a partial time period within each period of a potential of the electrode, and the second voltage value is supplied such that the first and second states are continuous.Type: GrantFiled: October 9, 2019Date of Patent: June 2, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Chishio Koshimizu, Shin Hirotsu
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Publication number: 20200118794Abstract: A plasma processing apparatus includes: a processing container; an electrode that places a workpiece thereon; a plasma generation source that supplies plasma into the processing container; a bias power supply that supplies a bias power to the electrode; an edge ring disposed at a periphery of the workpiece; a DC power supply that supplies a DC voltage to the edge ring; a controller that executes a first control procedure in which the DC voltage periodically repeats a first state having a first voltage value and a second state having a second voltage value, the first voltage value is supplied in a partial time period within each period of a potential of the electrode, and the second voltage value is supplied such that the first and second states are continuous.Type: ApplicationFiled: October 9, 2019Publication date: April 16, 2020Applicant: TOKYO ELECTRON LIMITEDInventors: Chishio KOSHIMIZU, Shin HIROTSU
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Patent number: 9418863Abstract: Disclosed is an etching method for etching an etching target layer. The etching method includes: a first step of depositing a plasma reaction product on a mask layer made of an organic film formed on the etching target layer; and after the first step, a second step of etching the etching target layer. The mask layer includes a coarse region in which a plurality of openings are formed, and a dense region surrounding the coarse region. The mask layer exists more densely in the dense region than in the coarse region. The coarse region includes a first region and a second region positioned close to the dense region compared to the first region. In the second step of the etching method, a width of the openings in the first region becomes narrower than a width of the openings in the second region.Type: GrantFiled: May 12, 2015Date of Patent: August 16, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Shin Hirotsu, Yoshiki Igarashi, Tomonori Miwa, Hiroshi Okada
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Patent number: 9312105Abstract: Disclosed is a method for etching an insulation film of a processing target object. The method includes: in a first term, periodically switching ON and OFF of a high frequency power so as to excite a processing gas containing fluorocarbon and supplied into a processing container of a plasma processing apparatus; and in a second term subsequent to the first term, setting the high frequency power to be continuously turned ON so as to excite the processing gas supplied into the processing container. In one cycle consisting of a term where the high frequency is turned ON and a term where the high frequency power is turned OFF in the first term, the second term is longer than the term where the high frequency power is turned ON.Type: GrantFiled: June 4, 2015Date of Patent: April 12, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Akira Takahashi, Kei Nakayama, Yoshiki Igarashi, Shin Hirotsu
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Publication number: 20150371830Abstract: Disclosed is a method for etching an insulation film of a processing target object. The method includes: in a first term, periodically switching ON and OFF of a high frequency power so as to excite a processing gas containing fluorocarbon and supplied into a processing container of a plasma processing apparatus; and in a second term subsequent to the first term, setting the high frequency power to be continuously turned ON so as to excite the processing gas supplied into the processing container. In one cycle consisting of a term where the high frequency is turned ON and a term where the high frequency power is turned OFF in the first term, the second term is longer than the term where the high frequency power is turned ON.Type: ApplicationFiled: June 4, 2015Publication date: December 24, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Akira TAKAHASHI, Kei NAKAYAMA, Yoshiki IGARASHI, Shin HIROTSU
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Publication number: 20150332932Abstract: Disclosed is an etching method for etching an etching target layer. The etching method includes: a first step of depositing a plasma reaction product on a mask layer made of an organic film formed on the etching target layer; and after the first step, a second step of etching the etching target layer. The mask layer includes a coarse region in which a plurality of openings are formed, and a dense region surrounding the coarse region. The mask layer exists more densely in the dense region than in the coarse region. The coarse region includes a first region and a second region positioned close to the dense region compared to the first region. In the second step of the etching method, a width of the openings in the first region becomes narrower than a width of the openings in the second region.Type: ApplicationFiled: May 12, 2015Publication date: November 19, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Shin HIROTSU, Yoshiki IGARASHI, Tomonori MIWA, Hiroshi OKADA
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Patent number: 8097534Abstract: On an etching target film formed on a substrate, a three-layer resist is laminated. This three-layer resist includes an organic film and a resist film developed into a resist pattern. Through the resist pattern, the organic film is etched into a mask pattern through which the etching target film will be etched. The organic film is etched with plasma which is obtained by exciting a process gas containing carbon dioxide and hydrogen to the plasma state. This scheme makes it possible to form a high perpendicularity mask pattern in the organic film.Type: GrantFiled: August 8, 2008Date of Patent: January 17, 2012Assignee: Tokyo Electron LimitedInventors: Shuhei Ogawa, Shin Hirotsu
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Patent number: 7943523Abstract: A plasma etching method for plasma-etching an anti-reflective coating formed on a target object includes the step of placing the target object into a processing chamber having a first electrode and a second electrode provided while facing each other, the target object including an etching target film, the anti-reflective coating and a patterned photoresist film sequentially formed in that order on a substrate. The plasma etching method further includes the steps of introducing a processing gas into the processing chamber; generating a plasma by applying a high frequency power to one of the first electrode and the second electrode; and applying a DC voltage to one of the first electrode and the second electrode.Type: GrantFiled: February 22, 2007Date of Patent: May 17, 2011Assignee: Tokyo Electron LimitedInventors: Shin Hirotsu, Wakako Naito, Yoshinori Suzuki
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Publication number: 20090047794Abstract: [Object] It is an object of the present invention to provide a semiconductor device manufacturing method capable of forming a high perpendicularity mask pattern, which is laminated on an etching target film on a substrate, through a resist pattern formed from a resist film laminated on the organic film, for use as an etching mask for the etching target film. [Means for Solving the Problem] There is provided a step of etching an organic film in a multi-layered resist laminated on an etching target film on a substrate, the multi-layered resist including the organic film and a resist film having a resist pattern laminated on the organic film, by a plasma, which has been obtained by making a process gas containing carbon dioxide and hydrogen, along the resist pattern, so as to form a mask pattern for etching the etching target film.Type: ApplicationFiled: August 8, 2008Publication date: February 19, 2009Inventors: Shuhei Ogawa, Shin Hirotsu
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Patent number: 7465670Abstract: On a surface of a semiconductor wafer W, a SiCN film, a SiCOH film, a TEOS film, an antireflection film, and a resist film (ArF resist) as a mask are formed in turn. A via hole is formed by plasma etching the SiCOH film with a predetermined etching gas comprising a mixed gas, for example, CF4/CH2F2/N2/O2 mixed gas (not containing a rare gas such as an Ar gas). Thereby, the selection ratio between a low dielectric constant insulation film comprising a carbon containing silicon oxide and the resist can be improved. And at the same time, even when the hole has a minute diameter and a high aspect ratio, an inner wall surface of the hole can be formed in a satisfactory state.Type: GrantFiled: March 28, 2006Date of Patent: December 16, 2008Assignee: Tokyo Electron LimitedInventors: Shin Hirotsu, Shuhei Ogawa
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Publication number: 20080045031Abstract: A plasma etching method for plasma-etching an anti-reflective coating formed on a target object includes the step of placing the target object into a processing chamber having a first electrode and a second electrode provided while facing each other, the target object including an etching target film, the anti-reflective coating and a patterned photoresist film sequentially formed in that order on a substrate. The plasma etching method further includes the steps of introducing a processing gas into the processing chamber; generating a plasma by applying a high frequency power to one of the first electrode and the second electrode; and applying a DC voltage to one of the first electrode and the second electrode.Type: ApplicationFiled: February 22, 2007Publication date: February 21, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Shin HIROTSU, Wakako Naito, Yoshinori Suzuki
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Publication number: 20080020584Abstract: The method of manufacturing a semiconductor device according to the present invention includes a step of etching an organic film formed to be embedded in recesses in a low dielectric constant film which is made of a material containing silicon, carbon, oxygen, and hydrogen. The organic film is typically a sacrifice film formed on the low dielectric constant film to be embedded in recesses formed in the low dielectric constant for embedding electrodes therein. The etching is performed with plasma of a process gas containing carbon dioxide. With the method, the organic film can be etched while suppressing damage to the low dielectric constant film.Type: ApplicationFiled: March 20, 2007Publication date: January 24, 2008Inventors: Shin Hirotsu, Yoshinori Suzuki
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Publication number: 20060213866Abstract: On a surface of a semiconductor wafer W, a SiCN film, a SiCOH film, a TEOS film, an antireflection film, and a resist film (ArF resist) as a mask are formed in turn. A via hole is formed by plasma etching the SiCOH film with a predetermined etching gas comprising a mixed gas, for example, CF4/CH2F2/N2/O2 mixed gas (not containing a rare gas such as an Ar gas). Thereby, the selection ratio between a low dielectric constant insulation film comprising a carbon containing silicon oxide and the resist can be improved. And at the same time, even when the hole has a minute diameter and a high aspect ratio, an inner wall surface of the hole can be formed in a satisfactory state.Type: ApplicationFiled: March 28, 2006Publication date: September 28, 2006Applicant: TOKYO ELECTRON LIMITEDInventors: Shin Hirotsu, Shuhei Ogawa