Abstract: A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.

Abstract: A semiconductor memory device may be effectively evaluated by a test that compares the phase of an internally generated control signal with the phase of an internally generated clock signal. Specifically, if the phase of the internal data strobe signal IDQS is synchronized with the phase of the internal clock signal ICLK through the test, the data strobe signal DQS may also be synchronized with the external clock signal CLK. Thus, the test may prevent certain critical parameters, for example, AC parameter tDQSCK, from being out of an allowable range over PVT (process, voltage, and temperature variation). The test helps ensure that the semiconductor memory device will operate properly in read mode.

Abstract: A semiconductor memory device includes a write controller configured to transmit a first input data that is supplied through a first pad, to a first global I/O line and a second global I/O line when a write operation is executed in a test mode. The semiconductor memory device further includes a first write driver configured to store the first input data via the first global I/O line in a first cell block when the write operation is executed in the test mode. The semiconductor memory device further includes a first I/O line driver configured to supply signals to the first global I/O line and a first test I/O line in response to a first output data supplied from the first cell block when a read operation is executed in the test mode.

Abstract: A semiconductor memory device includes a transmission line configured to transmit a fuse enable signal for performance of a repair operation; a first repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a first repair enable signal for performing a repair operation for a first bank; and a second repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a second repair enable signal for performing a repair operation for a second bank.

Abstract: A semiconductor memory device may be effectively evaluated by a test that compares the phase of an internally generated control signal with the phase of an internally generated clock signal. Specifically, if the phase of the internal data strobe signal IDQS is synchronized with the phase of the internal clock signal ICLK through the test, the data strobe signal DQS may also be synchronized with the external clock signal CLK. Thus, the test may prevent certain critical parameters, for example, AC parameter tDQSCK, from being out of an allowable range over PVT (process, voltage, and temperature variation). The test helps ensure that the semiconductor memory device will operate properly in read mode.

Abstract: A driver circuit of a semiconductor apparatus includes a driver and a control unit configured to vary a voltage level of a power supply terminal of the driver in response to a standby mode signal.

Abstract: A semiconductor memory device includes a write controller configured to transmit a first input data that is supplied through a first pad, to a first global I/O line and a second global I/O line when a write operation is executed in a test mode. The semiconductor memory device further includes a first write driver configured to store the first input data via the first global I/O line in a first cell block when the write operation is executed in the test mode. The semiconductor memory device further includes a first I/O line driver configured to supply signals to the first global I/O line and a first test I/O line in response to a first output data supplied from the first cell block when a read operation is executed in the test mode.

Abstract: A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled.

Abstract: A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled.

Abstract: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

Abstract: A data transfer circuit includes a first driver configured to drive a first line with data, a pattern alteration unit configured to change a pattern of the data transferred through the first line and produce a pattern-changed data, a second driver configured to drive a second line with the pattern-changed data; and a pattern restoration unit configured to receive the pattern-changed data transferred through the second line and restore the pattern of the data before the pattern change.

Abstract: A semiconductor memory device includes a transmission line configured to transmit a fuse enable signal for performance of a repair operation; a first repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a first repair enable signal for performing a repair operation for a first bank; and a second repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a second repair enable signal for performing a repair operation for a second bank.

Abstract: A driver circuit of a semiconductor apparatus includes a driver and a control unit configured to vary a voltage level of a power supply terminal of the driver in response to a standby mode signal.

Abstract: A temperature data output circuit is provided which is capable of outputting a temperature signal which is enabled when an internal temperature of at least one of the semiconductor memory chips mounted on a multi chip package exceeds a predetermined temperature.

Abstract: An internal circuit protection circuit includes a voltage comparison unit and an internal circuit protection unit. The voltage comparison unit is configured to compare an external driving voltage applied from outside with a reference clamp voltage and output a comparison signal. The internal circuit protection unit is configured to adjust a level of the external driving voltage to a lower level than that of the reference clamp voltage, in response to the comparison signal.

Abstract: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

Abstract: A data transfer circuit includes a first driver configured to drive a first line with data, a pattern alteration unit configured to change a pattern of the data transferred through the first line and produce a pattern-changed data, a second driver configured to drive a second line with the pattern-changed data; and a pattern restoration unit configured to receive the pattern-changed data transferred through the second line and restore the pattern of the data before the pattern change.

Abstract: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

Abstract: In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.