Abstract: A method, of seeding an optical proximity correction (OPC) process, includes: receiving, at an input device of a computer, a subject pre-OPC design-signature for a subject pre-OPC design package; selecting, by the processor and via interaction with an OPC database operatively connected to the computer, one amongst archived post-OPC design packages based on relatedness between the subject pre-OPC design-signature and archived post-OPC design-signatures corresponding to the archived post-OPC design packages, and thereby retrieving the selected archived post-OPC design packages; and generating one or more seeds for the OPC process based on the selected archived post-OPC design package.

Abstract: A method, of seeding an optical proximity correction (OPC) process, includes: receiving, at an input device of a computer, a subject pre-OPC design-signature for a subject pre-OPC design package; selecting, by the processor and via interaction with an OPC database operatively connected to the computer, one amongst archived post-OPC design packages based on relatedness between the subject pre-OPC design-signature and archived post-OPC design-signatures corresponding to the archived post-OPC design packages, and thereby retrieving the selected archived post-OPC design packages; and generating one or more seeds for the OPC process based on the selected archived post-OPC design package.

Abstract: Methods and apparatus of performing layout-versus-layout (LVL) comparison are disclosed. A layout may be in various formats such as GDSII or OASIS, for different circuits, and represented by a basic layout element, a hierarchical cell or a plurality of independent cells in various layers. A basic layout element, a hierarchical cell, and a layout with a plurality of independent cells may have a signature generated according to the embodiment methods. The signature of a basic layout element may be generated based on values of a center and a circumference, and a hashed trace value generated by a hash function of a trace of the basic layout element. The signature of a hierarchical cell can be generated recursively. A signature of a first layout may be compared to a signature of a second layout to determine whether the first layout matches the second layout.

Abstract: Methods and apparatus of performing layout-versus-layout (LVL) comparison are disclosed. A layout may be in various formats such as GDSII or OASIS, for different circuits, and represented by a basic layout element, a hierarchical cell or a plurality of independent cells in various layers. A basic layout element, a hierarchical cell, and a layout with a plurality of independent cells may have a signature generated according to the embodiment methods. The signature of a basic layout element may be generated based on values of a center and a circumference, and a hashed trace value generated by a hash function of a trace of the basic layout element. The signature of a hierarchical cell can be generated recursively. A signature of a first layout may be compared to a signature of a second layout to determine whether the first layout matches the second layout.