Patents by Inventor Shin Hyun JEONG

Shin Hyun JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase mixing circuit and multi-phase clock signal alignment circuit including the same
    Patent number: 11881860
    Abstract: A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: January 23, 2024
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Shin-Hyun Jeong, Yongun Jeong, Suhwan Kim
  • PHASE MIXING CIRCUIT AND MULTI-PHASE CLOCK SIGNAL ALIGNMENT CIRCUIT INCLUDING THE SAME
    Publication number: 20230403000
    Abstract: A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.
    Type: Application
    Filed: November 17, 2022
    Publication date: December 14, 2023
    Inventors: Shin-Hyun JEONG, Yongun Jeong, Suhwan Kim
  • Semiconductor device for controlling voltage at an input node of a circuit during a low power mode
    Patent number: 11271549
    Abstract: A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 8, 2022
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Shin Hyun Jeong, Suhwan Kim, Gi Moon Hong, Ji Hyo Kang, Jae Hyeok Yang, Dae Han Kwon, Dong Hyun Kim
  • SEMICONDUCTOR DEVICE FOR CONTROLLING VOLTAGE AT AN INPUT NODE OF A CIRCUIT DURING A LOW POWER MODE
    Publication number: 20210328579
    Abstract: A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.
    Type: Application
    Filed: November 13, 2020
    Publication date: October 21, 2021
    Inventors: Shin Hyun JEONG, Suhwan KIM, Gi Moon HONG, Ji Hyo KANG, Jae Hyeok YANG, Dae Han KWON, Dong Hyun KIM