Patents by Inventor Shinichi Ishimoto

Shinichi Ishimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6996006
    Abstract: A memory mat is provided separately from a memory mat that is a normal memory area, and data therein cannot be read from the outside. In a page buffer, information input from the outside is stored. A comparing circuit compares security information stored in memory mat with information stored in page buffer, and the comparison result is output to the outside as a status. Even when unauthorized copying is performed, information in memory mat is not copied. Therefore, an external apparatus can easily determine whether or not the semiconductor memory is an unauthorized copy by referring to the status.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: February 7, 2006
    Assignees: Renesas Technology Corp., Renesas Solutions Corporation
    Inventors: Shinichi Ishimoto, Yoshikazu Miyawaki, Shinji Kawai, Atsushi Ohba
  • Patent number: 6839798
    Abstract: A flash memory includes an address information storage and a data write unit. The address information storage records address information about blank areas in a cluster consisting of a plurality of sectors. The data write unit writes, in response to a write request of data, data into at least one of the blank areas by referring to the address information about the blank areas. This makes it possible to solve a problem that occurs with a conventional flash memory. In particular, the number of erasable times of the improved flash memory is not limited to about one tenth of that of an EEPROM, and hence the improved flash memory can store frequently rewritten data.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: January 4, 2005
    Assignees: Renesas Technology Corp., Mitsubishi Electric Semiconductor Application Engineering Corp.
    Inventors: Hironao Nagayoshi, Shinichi Ishimoto
  • Publication number: 20040264262
    Abstract: A memory mat is provided separately from a memory mat that is a normal memory area, and data therein cannot be read from the outside. In a page buffer, information input from the outside is stored. A comparing circuit compares security information stored in memory mat with information stored in page buffer, and the comparison result is output to the outside as a status. Even when unauthorized copying is performed, information in memory mat is not copied. Therefore, an external apparatus can easily determine whether or not the semiconductor memory is an unauthorized copy by referring to the status.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 30, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Shinichi Ishimoto, Yoshikazu Miyawaki, Shinji Kawai, Atsushi Ohba
  • Publication number: 20040170060
    Abstract: A refresh zone detection part divides a block of a semiconductor memory into refresh zone units for executing refresh, and detects the refresh zone including the sector of the writing target. A refresh execution part sequentially refreshes the sectors included in the refresh zone detected by refresh zone detection part, every time data is written to a sector. Thus, it is possible to prevent the number of rewritings to a specific sector from increasing, and the refresh can prevent data change due to accumulative disturbance.
    Type: Application
    Filed: August 21, 2003
    Publication date: September 2, 2004
    Applicants: RENESAS TECHNOLOGY CORP., RENESAS SOLUTIONS CORPORATION
    Inventor: Shinichi Ishimoto