Patents by Inventor Shin-ichi Ogou

Shin-ichi Ogou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8085112
    Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; the length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 27, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Taras Kushta, Kaoru Narita, Tomoyuki Kaneko, Shin-ichi Ogou
  • Publication number: 20110279195
    Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; the length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.
    Type: Application
    Filed: July 21, 2011
    Publication date: November 17, 2011
    Applicants: RENESAS ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Taras KUSHTA, Kaoru NARITA, Tomoyuki KANEKO, Shin-ichi OGOU
  • Patent number: 8013685
    Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: September 6, 2011
    Assignees: Renesas Electronics Corporation, NEC Corporation
    Inventors: Taras Kushta, Kaoru Narita, Tomoyuki Kaneko, Shin-ichi Ogou
  • Publication number: 20090015345
    Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.
    Type: Application
    Filed: March 2, 2007
    Publication date: January 15, 2009
    Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATION
    Inventors: Taras Kushta, Kaoru Narita, Tomoyuki Kaneko, Shin-ichi Ogou
  • Patent number: 5493253
    Abstract: In an integrated circuit having first (VDD) and second (GND) power terminals, a differential amplifier has a load end connected to the first power terminal to produce-in response to an input signal (IN(1)-IN(2)) an output signal (OUT(1)-OUT(2)) when a common connected end of the amplifier is connected through an n-type constant current transistor (19) to the second power terminal. Connected between the power terminals, a bias resistor (25) and an n-type bias transistor (27) produces a bias circuit output voltage for comparison with a reference voltage (REF) by a voltage comparator (29) for producing a difference voltage which is delivered to a constant current transistor gate electrode and fed back to a bias transistor gate electrode to keep an amplitude of the output signal constant against a temperature variation. It is possible to use as the reference voltage a divided voltage of a source voltage supplied between the power terminals.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: February 20, 1996
    Assignee: NEC Corporation
    Inventor: Shin-ichi Ogou