Abstract: A variation measurement device for a physical activity includes a display element that displays a variation amount of a weight data from a benchmark of the weight data, which varies depending on the physical activity of the measurement subject.

Abstract: In a liquid chromatograph mass spectrometer (LC/MS) for performing mass spectrometry of fractionated samples prepared with a multi-dimensional LC or similar LC with high separatory capability, fractionated sample useful information which shows the degree of usefulness of various substances with respect to retention time is prepared from prior information which includes, for example, elution characteristics in the LC depending on the kind of column or other factors or the degree of ease of ionization in the MS. During a measurement, the preparative separation of an eluate and the preparation of fractionated samples are not performed within a period of time which has been judged to be useless based on the fractionated sample useful information. By selecting fractionated samples at each dimension of the multi-dimensional LC, the number of fractionated samples to be eventually subjected to mass spectrometry can be significantly reduced.

Abstract: A variation measurement device for a physical activity includes a display element that displays a variation amount of a weight data from a benchmark of the weight data, which varies depending on the physical activity of the measurement subject.

Abstract: In a liquid chromatograph mass spectrometer (LC/MS) for performing mass spectrometry of fractionated samples prepared with a multi-dimensional LC or similar LC with high separatory capability, fractionated sample useful information which shows the degree of usefulness of various substances with respect to retention time is prepared from prior information which includes, for example, elution characteristics in the LC depending on the kind of column or other factors or the degree of ease of ionization in the MS. During a measurement, the preparative separation of an eluate and the preparation of fractionated samples are not performed within a period of time which has been judged to be useless based on the fractionated sample useful information. By selecting fractionated samples at each dimension of the multi-dimensional LC, the number of fractionated samples to be eventually subjected to mass spectrometry can be significantly reduced.

Abstract: To enable accurate analysis of a base sequence even in an electrophoretic pattern containing a degraded part.

Abstract: Disclosed herein is a method for assessing the degree of reliability of a nucleic acid base sequence, by which a higher-accuracy assessment result of the degree of reliability can be obtained as compared to a case where the degree of reliability is assessed based on only the evaluation of analytical data. The method includes the steps: (A) when measured data is processed into analytical data, computing a processing evaluation value E1i for evaluating quality of measured data of an i-th base and contents of processing having been performed on the measured data of the i-th base; (B) computing an analytical data evaluation value E2i of the i-th base based on the processed analytical data; and (C) computing a degree of reliability by a predetermined calculation formula using the processing evaluation value E1i and the analytical data evaluation value E2i.

Abstract: To enable accurate analysis of a base sequence even in an electrophoretic pattern containing a degraded part.

Abstract: Disclosed herein is a method for assessing the degree of reliability of a nucleic acid base sequence, by which a higher-accuracy assessment result of the degree of reliability can be obtained as compared to a case where the degree of reliability is assessed based on only the evaluation of analytical data. The method includes the steps: (A) when measured data is processed into analytical data, computing a processing evaluation value E1i for evaluating quality of measured data of an i-th base and contents of processing having been performed on the measured data of the i-th base; (B) computing an analytical data evaluation value E2i of the i-th base based on the processed analytical data; and (C) computing a degree of reliability by a predetermined calculation formula using the processing evaluation value E1i and the analytical data evaluation value E2i.

Abstract: For automating the operation of an electrophoresis apparatus and improving the throughput, the present electrophoresis apparatus has two platens capable of controlling temperature of electrophoresis plates placed thereon, a loading medium charging unit for sending a loading medium under pressure, a loading medium charging nozzle mechanism having a pair of nozzles connected to the loading medium charging unit, a pipetter mechanism for dispensing samples to sample dispensing openings of the electrophoresis plates placed on the platens, a stacker mechanism for storing sample plates, a loading buffer solution supplying mechanism, a loading buffer solution dispensing mechanism connected to the loading buffer solution supplying mechanism, a power unit for allowing electrophoresis separation for each electrophoresis plate placed on the platens, and a detector for optically detecting components migrating through each electrophoresis flow channel of the electrophoresis plates.

Abstract: A power saving of a serial interface circuit decreases the unnecessary power consumption of a serial interface circuit, while decreasing the return time and expanding the power saving range. Gates are disposed for stopping the clock supply to a digital portion of the interface circuit while maintaining operation of clock sources in the digital portions. Therefore a quick shift to and return from the power save mode by stopping and restarting clocks is implemented, which further decreases power consumption.

Abstract: For automating the operation of an electrophoresis apparatus and improving the throughput, the present electrophoresis apparatus has two platens capable of controlling temperature of electrophoresis plates placed thereon, a loading medium charging unit for sending a loading medium under pressure, a loading medium charging nozzle mechanism having a pair of nozzles connected to the loading medium charging unit, a pipetter mechanism for dispensing samples to sample dispensing openings of the electrophoresis plates placed on the platens, a stacker mechanism for storing sample plates, a loading buffer solution supplying mechanism, a loading buffer solution dispensing mechanism connected to the loading buffer solution supplying mechanism, a power unit for allowing electrophoresis separation for each electrophoresis plate placed on the platens, and a detector for optically detecting components migrating through each electrophoresis flow channel of the electrophoresis plates.

Abstract: There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.

Abstract: A power saving of a serial interface circuit decreases the unnecessary power consumption of a serial interface circuit, while decreasing the return time and expanding the power saving range. Gates are disposed for stopping the clock supply to a digital portion of the interface circuit while maintaining operation of clock sources in the digital portions. Therefore a quick shift to and return from the power save mode by stopping and restarting clocks is implemented, which further decreases power consumption.

Abstract: There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.

Abstract: A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses.

Abstract: A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.

Abstract: An index buffer circuit and a translation look-aside buffer (TLB) are provided in an address unit of a vector processor unit. The index buffer circuit incudes a plurality of buffers, an input pointer generating unit for generating an input control signal indicating which selected buffer in a buffer portion, index data shall be stored, and an output pointer generating unit for outputting a control signal indicated from which selected buffer in the buffer portion output data is to be read. The TLB translates a logical address to a physical address upon receipt of the output from the index buffer. The TLB has a least recently used (LRU) flag register which can maintain the priority even if the entries are reset and thus the entries of the TLB can be used as buffers when the vector processor unit operates as a bus slave.