Patents by Inventor Shin-ichiro Akiyama

Shin-ichiro Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5872994
    Abstract: In a microcomputer comprising internal buses, a serial communication interface, a flash memory, a RAM, a ROM for storing a writing program, an input/output port, a CPU, and a mode control unit for setting various operation modes and test modes in the microcomputer, a switching circuit is connected between the ROM and the internal buses and between the input/output port and the internal buses. The mode control unit operates the switching circuit in an emulation test mode so that the ROM is deactivated and the input/output port is activated. Then, the CPU reads a program from the serial communication interface and writes the program into the flash memory in accordance with a writing program from the input/output port.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: February 16, 1999
    Assignee: NEC Corporation
    Inventors: Shin-Ichiro Akiyama, Sadahiro Yasuda, Yuichi Iizuka, Hiroaki Nishimoto, Yuuichi Osada
  • Patent number: 5534799
    Abstract: In a flag control circuit successively supplied with first and second input flag signals produced in relation to first and second results of calculations in an arithmetic and logic unit to produce a final output flag signal, the first input flag signal is latched by a primary flag signal latching circuit while the second input flag signal is latched by the secondary flag signal latching circuit. The first latched flag signal and the second latched flag signal are ANDed by an AND gate circuit to produce the final output flag signal.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: July 9, 1996
    Assignee: NEC Corporation
    Inventor: Shin-Ichiro Akiyama
  • Patent number: 5361290
    Abstract: A basic clock signal generating circuit for use in a single chip microcomputer includes a frequency divider receiving an external clock signal for generating a frequency-divided clock signal, and a waveform shaping circuit receiving the frequency-divided clock signal output so as to generate a waveform-shaped frequency-divided clock as a basic clock of single chip microcomputer. An original oscillation clock generation circuit receives the external clock signal and generates an original oscillation clock having a frequency which is a-double of that of the basic clock. The basic clock and the original oscillation clock can be supplied to a peripheral circuit so that either the basic clock or the original oscillation clock can be selectively used in an internal circuit of the peripheral circuit.
    Type: Grant
    Filed: May 13, 1992
    Date of Patent: November 1, 1994
    Assignee: NEC Corporation
    Inventor: Shin-ichiro Akiyama