Abstract: A solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus are provided that are capable of reducing memory circuits of a column reading system, so that the column reading system can achieve a reduced layout area and eventually a reduced size. A column reading circuit includes an AD converting part and a calculating part. The AD converting part is configured to analog-to-digital convert a read-out reset signal and a read-out signal of a pixel signal read to a vertical signal line into an n-bit digital pixel signal. The calculating part includes an n-bit asynchronous counter including a retention circuit with a control logic function, which is configured to obtain a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part.

Abstract: A solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus are provided that are capable of reducing memory circuits of a column reading system, so that the column reading system can achieve a reduced layout area and eventually a reduced size. A column reading circuit includes an AD converting part and a calculating part. The AD converting part is configured to analog-to-digital convert a read-out reset signal and a read-out signal of a pixel signal read to a vertical signal line into an n-bit digital pixel signal. The calculating part includes an n-bit asynchronous counter including a retention circuit with a control logic function, which is configured to obtain a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part.

Abstract: A solid-state imaging device 10 includes a pixel portion 20 in which a plurality of pixels including photodiodes are arranged in rows and columns, a reading part 90 for reading pixel signals from the pixel portion, and a key generation part 82 which generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.

Abstract: This solid-state imaging device 100 has: a photosensitive part that includes pixel portions 211, which are disposed in a matrix, and charge transfer parts 212 for transferring, by the column, the signal charge of the pixel portions; a plurality of charge storage parts 220 that accumulate the signal charges transferred by the plurality of charge transfer parts of the photosensitive part; a relay part 240 that relays the transfer of the signal charges transferred by the plurality of charge transfer parts to each charge storage part; an output part 230 that outputs the signal charges of the plurality of charge storage parts as electric signals; a first substrate 110 at which the photosensitive unit 210 is formed; and a second substrate 120 at which the charge storage part 220 and output unit 230 are formed.

Abstract: A solid state imaging device has: a photosensitive part containing a plurality of charge transfer parts that transfer, in column units, the signal charges of a plurality of photoelectric conversion elements disposed in a matrix; a conversion/output unit that converts, to an electrical signal, the signal charges forwarded by the charge transfer parts; a peripheral circuit part that performs a predetermined process with respect to the electrical signals from the conversion/output part; a relay part that relays the forwarding to the peripheral circuit part of the electrical signal from the conversion/output part; a first substrate where a photosensitive part and the conversion/output part are formed; and a second substrate where the peripheral circuit part is formed. The first and second substrates are stacked together, and the relay part electrically connects the conversion/output part formed at the first substrate to the peripheral circuit part formed at the second substrate.

Abstract: A solid-state imaging device 10 includes a pixel portion 20 in which a plurality of pixels including photodiodes are arranged in rows and columns, a reading part 90 for reading pixel signals from the pixel portion, and a key generation part 82 which generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.

Abstract: A solid state imaging device has: a photosensitive part containing a plurality of charge transfer parts that transfer, in column units, the signal charges of a plurality of photoelectric conversion elements disposed in a matrix; a conversion/output unit that converts, to an electrical signal, the signal charges forwarded by the charge transfer parts; a peripheral circuit part that performs a predetermined process with respect to the electrical signals from the conversion/output part; a relay part that relays the forwarding to the peripheral circuit part of the electrical signal from the conversion/output part; a first substrate where a photosensitive part and the conversion/output part are formed; and a second substrate where the peripheral circuit part is formed. The first and second substrates are stacked together, and the relay part electrically connects the conversion/output part formed at the first substrate to the peripheral circuit part formed at the second substrate.

Abstract: This solid-state imaging device 100 has: a photosensitive part that includes pixel portions 211, which are disposed in a matrix, and charge transfer parts 212 for transferring, by the column, the signal charge of the pixel portions; a plurality of charge storage parts 220 that accumulate the signal charges transferred by the plurality of charge transfer parts of the photosensitive part; a relay part 240 that relays the transfer of the signal charges transferred by the plurality of charge transfer parts to each charge storage part; an output part 230 that outputs the signal charges of the plurality of charge storage parts as electric signals; a first substrate 110 at which the photosensitive unit 210 is formed; and a second substrate 120 at which the charge storage part 220 and output unit 230 are formed.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each image pixel arranged along a column may be coupled to a pixel column line. Each pixel column line may be coupled to column memory circuitry via a respective analog-to-digital converter circuit. The column memory circuitry may include multiple column memory circuits, including a spare column memory circuit. If none of the column memory circuits are defective, the spare column memory circuit is idle. If one of the column memory circuits is defective, the spare column memory circuit is engaged to bypass the defective column memory circuit. Configured in this way, the column memory circuitry is provided with column-wise memory repair capabilities.

Abstract: An imaging system may include image processing circuitry and an image sensor having a pixel, readout circuitry, and control circuitry. The pixel may have a dual conversion gain gate for switching between a high conversion gain mode and a low conversion gain mode. The pixel may capture a first image signal while the dual conversion gain gate is turned of and a second image signal subsequent to capturing the first image signal while the dual conversion gain gate is turned on. The readout circuitry may identify a selected one of the first and second image signals to output to the image processing circuitry based on the first image signal. In this way, the readout circuitry may output a low conversion gain signal when saturating charge is stored on the charge storage region and may output a high conversion gain signal when insufficient charge is stored on the charge storage region.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each image pixel arranged along a column may be coupled to a pixel column line. Each pixel column line may be coupled to column memory circuitry via a respective analog-to-digital converter circuit. The column memory circuitry may include multiple column memory circuits, including a spare column memory circuit. If none of the column memory circuits are defective, the spare column memory circuit is idle. If one of the column memory circuits is defective, the spare column memory circuit is engaged to bypass the defective column memory circuit. Configured in this way, the column memory circuitry is provided with column-wise memory repair capabilities.

Abstract: An imaging system may include image processing circuitry and an image sensor having a pixel, readout circuitry, and control circuitry. The pixel may have a dual conversion gain gate for switching between a high conversion gain mode and a low conversion gain mode. The pixel may capture a first image signal while the dual conversion gain gate is turned of and a second image signal subsequent to capturing the first image signal while the dual conversion gain gate is turned on. The readout circuitry may identify a selected one of the first and second image signals to output to the image processing circuitry based on the first image signal. In this way, the readout circuitry may output a low conversion gain signal when saturating charge is stored on the charge storage region and may output a high conversion gain signal when insufficient charge is stored on the charge storage region.

Abstract: An image sensor may be provided that includes an image pixel array, analog column circuitry and digital column circuitry. The digital column circuitry may extract a systematic analog signal offset from data received from the analog column circuitry. The digital column circuitry may generate analog signal offset correction values based on the systematic analog signal offsets and provide the analog signal offset correction values to the analog column circuitry. The analog column circuitry may remove signal offsets from subsequently read out image data from the image pixel array using the analog signal offset correction values provided by the digital column circuitry. The image pixel array may include image pixels having color filters of various colors. The digital column circuitry may generate analog signal offset correction values corresponding to each of the various colors.

Abstract: An imaging system may include an image sensor array and column randomizing multiplexers. The imaging system may include a data output circuit and image readout circuitry such as analog amplifiers, analog-to-digital converters, and memory circuits. The column randomizing multiplexers may include a first column randomizing multiplexer between the image sensor array and at least some of the image readout circuitry. The first column randomizing multiplexer may randomly connect columns of the image sensor array to the image readout circuitry. The connections made by the first column randomizing multiplexer may be randomized as each row of the image sensor array is read out. The column randomizing multiplexers may include a second column randomizing multiplexer between at least some of the image readout circuitry and the data output circuit. The second column randomizing multiplexer may reorder image data for the image readout circuitry.

Abstract: An image sensor may be provided that includes an image pixel array, analog column circuitry and digital column circuitry. The digital column circuitry may extract a systematic analog signal offset from data received from the analog column circuitry. The digital column circuitry may generate analog signal offset correction values based on the systematic analog signal offsets and provide the analog signal offset correction values to the analog column circuitry. The analog column circuitry may remove signal offsets from subsequently read out image data from the image pixel array using the analog signal offset correction values provided by the digital column circuitry. The image pixel array may include image pixels having color filters of various colors. The digital column circuitry may generate analog signal offset correction values corresponding to each of the various colors.

Abstract: An imaging system may include an image sensor array and column randomizing multiplexers. The imaging system may include a data output circuit and image readout circuitry such as analog amplifiers, analog-to-digital converters, and memory circuits. The column randomizing multiplexers may include a first column randomizing multiplexer between the image sensor array and at least some of the image readout circuitry. The first column randomizing multiplexer may randomly connect columns of the image sensor array to the image readout circuitry. The connections made by the first column randomizing multiplexer may be randomized as each row of the image sensor array is read out. The column randomizing multiplexers may include a second column randomizing multiplexer between at least some of the image readout circuitry and the data output circuit. The second column randomizing multiplexer may reorder image data for the image readout circuitry.

Abstract: A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting the average number of branches and the number of stages design constraints.

Abstract: A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting the average number of branches and the number of stages design constraints.

Abstract: A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting the average number of branches and the number of stages design constraints.

Abstract: A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting the average number of branches and the number of stages design constraints.