Abstract: An error correcting and detecting apparatus for a CD-ROM or DVD system executes a high speed decode process. The apparatus includes an input interface, a temporary memory, a correcting circuit, a detecting circuit, a principal memory, and an output interface. The input interface fetches digital data in a block by block manner. The temporary memory stores the fetched digital data in a block by block manner. The correcting circuit performs error correction on digital data read from the temporary memory in a block by block manner using the error correction code and rewrites erroneous digital data to the temporary memory with the corrected digital data. The detecting circuit performs error detection on the error corrected digital data and supplied from the temporary memory in a block by block manner using the error detection code and sets an error flag based on a detection result.

Abstract: The present invention relates to an error correcting and detecting apparatus that executes a decode process at high speed. The error correcting and detecting apparatus receives digital data including an error correction code and an error detection code and performs error correction and error detection on the digital data.

Abstract: An error correction decoder for correcting errors in digital data includes an address generation circuit capable of generating addresses for accessing a first buffer memory and a second buffer memory. The first buffer memory preferably stores user data, and the second buffer memory stores parity code data associated with the user data. An input controller receives input data and stores the input data in the first and second buffer memories in accordance with the addresses generated by the address generation circuit. An error correction circuit receives user data and associated parity code data, performs error correction, and rewrites the corrected data and parity code data back to the respective memory areas. An output controller then read the error-corrected user data from the first buffer memory.

Abstract: An apparatus for reproducing original image data from compressed image data, supplied thereto as a plurality of separate data blocks, each data block including a plurality of compressed pixel data arranged in a matrix form of rows and columns. The apparatus includes a reproducing circuit for sequentially reproducing a plurality of original pixel data, block by block, by subjecting the compressed pixel data of each data block to data expansion; and a Differential Pulse Code Modulation (DPCM) encoder, coupled to the reproducing circuit, for performing DPCM encoding on each reproduced pixel data supplied from the reproducing circuit to sequentially produce a plurality of DPCM code data. The apparatus further includes an image memory, coupled to the DPCM encoder, for storing the DPCM code data supplied from the DPCM encoder.