Abstract: A pipelined multi-stage analog-to-digital converter (ADC) exhibits high speed and high resolution characteristics in a small chip area using a CMOS process. An optimized high resolution multi-stage ADC improves integral non-linearity errors (INL) and differential non-linearity (DNL) errors and hence increases yield. A binary-weighted capacitor array is used in a multiplying digital-to-analog converter (MDAC) in a front-end stage, and a unit capacitor array is used in the MDACs of the latter stages thereof. Offset, feedthrough and gain errors are removed via digital correction. A digital calibration technique is adopted to reduce the non-ideal effects resulting from component mismatch, by measuring all the code errors of the front-end stage, to thereby minimize the midpoint code DNL error without reference to code symmetry.