Abstract: In a reference clock signal generator for generating a sampled servo format reference clock signal using a PLL circuit, an unique distance is detected by an output signal of a VCO in a state the PLL circuit is operated based on a clock signal which corresponds to a number of rotations of a disk in generating the reference clock signal. When the unique distance is detected, a dividing ratio of a frequency divider is changed to operate the PLL circuit based on a clock mark detecting signal. The dividing ratio is set so that an oscillation frequency of the VCO becomes constant before and after switching from the clock signal that corresponds to the number of rotations of the disk to the clock mark signal. A count of the frequency divider is preset to zero with the first clock mark signal after the detection of the unique distance and the detection of the clock marks thereafter is carried out based on the count of the frequency divider.