Abstract: Normal+Times New Roman, Justified, Line spacing: 1.5 lines A method for forming a dual damascene pattern is provided. According to the method, a diffusion barrier layer and an interlayer insulation layer are formed on a substrate. A surface of the interlayer insulation layer is processed to reduce adhesion and deformation. A capping layer is then formed on the interlayer insulation layer. Subsequently, the capping layer and the interlayer insulation layer are patterned to form a via hole, and the via hole is filled with a light absorption layer. After a photoresist pattern for a trench is formed on the light absorption layer, exposed portions of the light absorption layer, the interlayer insulation layer, and the capping layer are etched to a predetermined depth to form a trench. Then the photoresist pattern for the trench and the light absorption layer remaining in the via hole are removed.

Abstract: A MOS or CMOS device includes a substrate with an active area, a gate oxide layer on the substrate, a gate on the gate oxide layer, first sidewalls on sides of the gate, the first sidewalls contacting the gate oxide layer, spacers formed outside the second sidewalls, and a salicide layer formed by depositing a metal layer on the gate and the active area of the substrate and annealing the deposited metal layer.