Abstract: An apparatus for coding keys of graphic animation data and a method thereof are provided. The coding apparatus for encoding key data corresponding to time variables among graphic animation comprises a quantizer which quantizes the key data and generates quantized data; a differential pulse code modulation (DPCM) processing unit which DPCM processes the quantized data, receives the DPCM processed data, and by repeatedly performing DPCM processing, selects and outputs DPCM data having the lowest dispersion among N-th order DPCM data generated in the DPCM processing; a polar value removing unit which reduces the range of data by removing a polar value in the DPCM data output form the DPCM processing unit; and an entropy encoder which removes the redundancy of binary bits in the data output from the polar value removing unit and generates a compressed and encoded binary bit stream.

Abstract: A semiconductor device including a built-in redundancy analysis (BIRA) circuit for simultaneously testing and analyzing failures of a plurality of memories, and a failure analyzing method, includes a plurality of memory blocks, a plurality of built-in redundancy analysis units for outputting a group of failure repairing information signals by testing and analyzing a corresponding memory block among the plurality of memory blocks in response to common driving signals and each of independent selection signals, and a controller for generating the common driving signals and the respective independent selection signals in response to a plurality of externally applied control signals and sequentially receiving and sequentially outputting the group of failure repairing information signals generated from the respective built-in redundancy analysis units.

Abstract: A semiconductor integrated circuit including a plurality of cores and/or a plurality of user defined logic (UDL) circuits, also includes a scan signal converting circuit to generate a plurality of scan signals to test the cores and/or the circuits adopting various scan styles in core-based design. The scan signal converting circuit converts scan signals corresponding one of the scan styles into various scan signals to control shift and normal operation of the embedded plural cores and/or the UDL circuits. As a result, the integrated circuit having a plurality of cores and/or the UDL circuits can be tested by the generated various scan signals from the scan signal converting circuit, under control of the scan signals corresponding to one of the scan styles. Therefore, the integrated circuit can easily perform test algorithms such as automatic test-pattern generation (ATPG) algorithm, and the like.

Abstract: A memory address generator having a small chip area, a method for generating a memory address and a SRAM built-in self test (BIST) circuit using the same are described. When the number of addresses of a memory to be tested is 2.sup.n, where n is the number of bits in an address, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses, and an inverter for inverting the first address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to a control signal, to output the selected address as an address of the memory. When the number of addresses of the memory to be tested is not 2.sup.

Abstract: A semiconductor memory device with a built-in self test (BIST) circuit is disclosed including: a plurality of memory blocks; a plurality of selectors for selecting an address, a control signal and data of each memory block to a normal mode or a test mode in response to a BIST mode signal; a plurality of background generators for generating data to be written in each memory block and comparing data; a plurality of comparators for comparing data read from each memory block with the comparing data in response to the BIST mode signal and for generating a comparative result; a combination circuit for combining outputs of the plurality of comparator and for generating a test result; and a test controller for supplying a test address and a control signal to the plurality of selectors, for supplying a background number and an output inversion control signal to the plurality of background generators, and for supplying a comparing control signal to the plurality of comparators.