Abstract: Provided is a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM), including a first operation and a second operation. The first operation has the steps of partitioning partial products into a least significant part (LSP) and a most significant part (MSP), estimating a carry of the LSP, computing the MSP based on the estimated carry, computing the LSP independently to obtain a true carry and detecting a computation error by comparing the estimated carry with the true carry. Also, the second operation has the step of correcting the computation error based on the difference between the estimated carry and the true carry. Further, a VLSBM for processing pipelined data is also provided.

Abstract: Provided is a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM), including a first operation and a second operation. The first operation has the steps of partitioning partial products into a least significant part (LSP) and a most significant part (MSP), estimating a carry of the LSP, computing the MSP based on the estimated carry, computing the LSP independently to obtain a true carry and detecting a computation error by comparing the estimated carry with the true carry. Also, the second operation has the step of correcting the computation error based on the difference between the estimated carry and the true carry. Further, a VLSBM for processing pipelined data is also provided.

Abstract: A transpose unit of an apparatus comprises a plurality of banks each having a plurality of storage units, a write circuit, a plurality of selectors, and a parallel-to-serial circuit. The write circuit is configured to perform selections on the plurality of banks for storing data from a source memory. Each selector comprises an output and a plurality of inputs respectively coupled with the plurality of storage units of a corresponding bank, and the outputs of the plurality of selectors connect in parallel with the parallel-to-serial circuit. The parallel-to-serial circuit has a serial output connecting to a destination memory.

Abstract: A method for determining a logarithmic functional unit comprises providing a segment number; using the segment number to determine a piecewise linear approximation on a plurality of corresponding intervals for approximating a function for converting a fraction; providing a bit precision; converting endpoints separating the plurality of intervals to corresponding binary endpoints separating an additional plurality of intervals in the bit precision; determining an adjusted piecewise linear approximation that has an approximation error less than a threshold and is on the additional plurality of intervals; encoding coefficients of the adjusted piecewise linear approximation; determining a less precise approximation from the adjusted piecewise linear approximation as a candidate linear approximation, wherein the less precise approximation uses an argument value having a least bit-width while still being able to have an approximation error less than the threshold; and implementing the less precise approximation to

Abstract: A multitasking processor and a task switching method thereof are provided. The task switching method includes following steps. A first task is executed by the multitasking processor, wherein the first task contains a plurality of switching-point instructions. An interrupt event occurs. Accordingly, the multitasking processor temporarily stops executing the first task and starts to execute a second task. The multitasking processor executes a handling process of the interrupt event and sets a switching flag. After finishing the handling process of the interrupt event, the multitasking processor does not perform task switching but continues to execute the first task, and the multitasking processor only performs task switching to execute the second task when it reaches a switching-point instruction in the first task.

Abstract: A new method is provided to monitor and to prevent IMD oxide irregularities such as IMD oxide cracks. A monitoring pattern is inserted in the test line of the fabrication substrate to monitor the strength of the created layer of IMD oxide. Variations in the characteristics of the created layer of IMD oxide can in this manner be detected. In addition, design rules are provided that are aimed at avoiding layers of IMD oxide that have proven or are known to be particularly prone to the occurrence of IMD oxide cracks.

Abstract: Within each of a pair of methods for forming each of a pair of microelectronic fabrications with reduced cracking within each of a pair of silicon oxide dielectric layers there is employed at least one stress reducing layer. The at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material, such as a silicon nitride dielectric material or a silicon oxynitride dielectric material.

Abstract: Within each of a pair of methods for forming each of a pair of microelectronic fabrications with reduced cracking within each of a pair of silicon oxide dielectric layers there is employed at least one stress reducing layer. The at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material, such as a silicon nitride dielectric material or a silicon oxynitride dielectric material.