Abstract: The present invention relates to a three-dimensional reconstructing method of a 2D medical image. A three-dimensional reconstructing device includes: a communicator for receiving sequential 2D images with an arbitrary slice gap; a sliced image generator for generating at least one sliced image positioned between the 2D images based on a feature point of the adjacent 2D images; and a controller for reconstructing the 2D image into a 3D image by use of the generated sliced image and providing the 3D image.

Abstract: The present disclosure discloses systems and methods of calculating a near-maximum likelihood detection (MLD) performance capability signal to interference plus noise ratio (SINR) according to instructions stored in non-transitory computer readable memory that when executed by a processor of a multiple-input, multiple output orthogonal frequency-division multiplexing (MIMO-OFDM) wireless communications receiver device cause the processor to perform operations including the processor acquiring Hi and noise variance ?n2 for each subcarrier of a set of subcarriers between a MIMO-OFDM wireless communications transmitter device and the wireless communications receiver device, computing an average received bit mutual information rate (RBIR) over all subcarriers, converting the average RBIR to an effective SINR; and selecting a modulation coding scheme (MCS).

Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.

Abstract: According to an embodiment, a method of allocating a job to a user comprising: receiving an allocation request signal from a terminal of the user; determining job processing information related to a job processed by the user; allocating at least one job among a plurality of jobs to the user based on the job processing information; and transmitting allocation information indicating the allocated at least one job to the terminal in response to the reception of the allocation request signal may be provided. According to an embodiment, a job allocation apparatus for performing the above-described job allocation method may also be provided. According to an embodiment, a computer readable recording medium containing a computer program for performing job allocation method may be provided.

Abstract: In some embodiments, a memory system includes a memory device and a host configured to transmit, to the memory device, a command and address (C/A) signal and a clock signal, and to transmit or receive data signals to or from the memory device. Each command that is configured to access the memory device is associated with an access timing parameter. The memory device includes an access parameter timer configured to measure an actual timing value of the access timing parameter, a spec register configured to provide a spec timing value defining an effective timing of the access timing parameter, a comparison circuit configured to compare the actual timing value and the spec timing value, and a mode register configured to store an access timing violation flag that is read by the host when the actual timing value deviates from the spec timing value by exceeding a predetermined range.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: A method performed by a transmitter in a wireless local area network (WLAN) is provided. The method comprises: setting a second parameter in a second frame based on a first puncturing pattern indicated by a first parameter in a first frame for a basic service set (BSS) set up by an access point (AP); and transmitting, to a receiver, the second frame, wherein the first puncturing pattern is one of a plurality of puncturing patterns pre-determined for a third parameter in a third frame.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells and a control logic circuit configured to control the semiconductor memory device. The control logic circuit includes a mode register and a remaining lifetime calculating device configured to count usage metrics based on one or more of the following: a number of clock signals received from a memory controller, an amount of data transmitted or received to or from the memory controller, and/or a number of commands received from the memory controller. The remaining lifetime calculating device generates a remaining lifetime code representing a remaining lifetime of the semiconductor memory device based on the usage metrics, and stores the remaining lifetime code in the mode register.

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.

Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.

Abstract: A method of an electronic apparatus for providing information related to a fulfillment center includes confirming data request information for requesting data related to the fulfillment center, acquiring first data corresponding to the data request information from at least one other apparatus connected to the electronic apparatus, and generating second data by processing the first data based on template information corresponding to the data request information.

Abstract: The present disclosure provides a computerized method for package management, including: storing, in a data structure, information of a seller in association with a plurality of items sold by the seller; receiving an indication of a transaction, the transaction indication including an address of a customer and at least one item identifier corresponding to an item sold by the seller; converting the transaction indication into a shipment request by formatting the transaction indication according to a standardized format required by a shipper; generating a message containing the formatted shipment request; transmitting the message to the shipper in real time to initialize shipment of the item; and providing real time confirmation to the seller and the customer that shipment has been initialized.

Abstract: The present disclosure relates to a method of loading data. The method includes checking a topic corresponding to a search word among a plurality of topics in response to acquiring a search word for a topic of a distributed messaging system from a user, checking a data format including one or more fields of a message loaded into a topic, and then loading data generated based on the checked data format and the read message into a data lake.

Abstract: The present invention relates to a solar cell having an edge collecting electrode and a solar cell module comprising the same, the solar cell being capable of preventing a cell crack phenomenon caused by an interconnector and improving an adhesive characteristic of the interconnector by dividing a planar area of the solar cell into a main area and an edge area and positioning the outermost contact point of the interconnector at a boundary between the main area and the edge area, and being capable of improving carrier collecting efficiency by arranging, in the edge area, the edge collecting electrode and the branched electrode which are physically separated from the interconnector.

Abstract: A femtosecond laser source according to an embodiment of the present invention includes: a pulse generator that converts a continuous wave laser into an optical pulse train; a burst generator that separates the optical pulse train into a plurality of burst pulses; a pulse amplification and spectral broadening unit that expands the spectrum by amplifying a plurality of burst pulses; and a pulse compressor that compresses a plurality of amplified burst pulses to generate a femtosecond laser with a pulse width of 1 picosecond (10?12 s) or less.

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.

Abstract: The flying object according to one embodiment comprises: a main body; a main wing formed on a side surface of the main body; a duct-shaped first propulsion part which is provided outside the main wing and can be tilted; a second propulsion part arranged behind the main body; horizontal tail wings formed on both side surfaces of the second propulsion part; and a control part for controlling the movement of the first propulsion part, second propulsion part, and horizontal tail wings, wherein the control part controls the second propulsion part and the horizontal tail wings according to the tilt angle of the first propulsion part.

Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.