Patents by Inventor Shin Kokura
Shin Kokura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9208037Abstract: The present invention provides a duplexed operation processor control system that includes operation processors, an I/O device, and at least one communication path that couples the operation processors to the I/O device, and at least one communication path that couples the operation processors with each other. The duplexed operation processor control system switches over either of the operation processors to be a primary operation processor that executes a control operation for a control target, and the other to be a secondary operation processor that is in a stand-by state, and the secondary operation processor snoops control data synchronously when the primary operation processor acquires the control data from the control target.Type: GrantFiled: June 18, 2009Date of Patent: December 8, 2015Assignees: HITACHI, LTD., HITACHI INDUSTRY & CONTROL SOLUTIONS, LTD.Inventors: Toshiki Shimizu, Akira Bando, Yusaku Otsuka, Yasuhiro Kiyofuji, Eiji Kobayashi, Akihiro Onozuka, Satoru Funaki, Masakazu Ishikawa, Hideaki Masuko, Yusuke Seki, Wataru Sasaki, Naoya Mashiko, Akihiro Nakano, Shin Kokura, Shoichi Ozawa, Yu Iwasaki
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Patent number: 8671300Abstract: A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.Type: GrantFiled: November 3, 2010Date of Patent: March 11, 2014Assignee: Hitachi, Ltd.Inventors: Noritaka Matsumoto, Tsutomu Yamada, Eiji Kobayashi, Akihiro Ohashi, Shin Kokura
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Patent number: 8493927Abstract: In a control apparatus which transmits/receives data from a central processing unit via a serial transfer channel to a communication control unit, and groups/distributes data of input/output units from the communication control unit via a parallel transfer channel, the control apparatus initiates a diagnosing unit of the parallel transfer channel in response to an instruction issued from the central processing unit, and diagnosis the input/output units subsequent to the diagnosis of the transmission channel. Data input/output timing of the input/output unit is also instructed from the central processing unit, so that the central processing unit can suppress lowering of response speeds caused by the diagnoses, and can maintain the periodicity of the data input/output.Type: GrantFiled: June 28, 2007Date of Patent: July 23, 2013Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.Inventors: Akira Bandou, Masamitsu Kobayashi, Masahiro Shiraishi, Akihiro Onozuka, Takashi Umehara, Shin Kokura, Eiji Kobayashi, Masakazu Ishikawa, Yasuyuki Furuta, Naoya Mashiko, Satoru Funaki, Yuusuke Seki, Tatsuyuki Ootani, Wataru Sasaki, Yusaku Otsuka, Akihiro Nakano, Shoichi Ozawa, Takenori Kasahara, Yu Iwasaki
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Patent number: 8423681Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.Type: GrantFiled: December 6, 2011Date of Patent: April 16, 2013Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd., Hitachi Engineering & Services Co., Ltd.Inventors: Yusaku Otsuka, Naoya Mashiko, Shin Kokura, Yu Iwasaki, Ryuichi Murakawa, Akira Bando, Wataru Sasaki, Hideyuki Yoshikawa, Masamitsu Kobayashi
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Patent number: 8255769Abstract: A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection.Type: GrantFiled: January 6, 2010Date of Patent: August 28, 2012Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.Inventors: Satoru Funaki, Yasuhiro Kiyofuji, Masashi Suenaga, Shin Kokura, Eiji Kobayashi, Akihiro Onozuka, Yusuke Seki, Toshiki Shimizu, Yukiko Tahara, Yuta Sugimoto
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Patent number: 8209594Abstract: A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections.Type: GrantFiled: October 8, 2010Date of Patent: June 26, 2012Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.Inventors: Akihiro Onozuka, Masakazu Ishikawa, Masamitsu Kobayashi, Takashi Umehara, Shin Kokura, Hiromichi Endoh, Satoru Funaki, Hisao Nagayama, Masahiro Shiraishi, Akira Bando, Eiji Kobayashi, Yasuyuki Furuta, Naoya Mashiko
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Publication number: 20120124268Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.Type: ApplicationFiled: December 6, 2011Publication date: May 17, 2012Inventors: Yusaku Otsuka, Naoya Mashiko, Shin Kokura, Yu Iwasaki, Ryuichi Murakawa, Akira Bando, Wataru Sasaki, Hideyuki Yoshikawa, Masamitsu Kobayashi
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Patent number: 8161362Abstract: Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.Type: GrantFiled: June 7, 2006Date of Patent: April 17, 2012Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.Inventors: Akira Bando, Shin Kokura, Takashi Umehara, Masamitsu Kobayashi, Hisao Nagayama, Naoya Mashiko, Masakazu Ishikawa, Masahiro Shiraishi, Akihiro Onozuka, Hiromichi Endoh, Tsutomu Yamada, Satoru Funaki
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Patent number: 8095695Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.Type: GrantFiled: January 23, 2009Date of Patent: January 10, 2012Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd., Hitachi Engineering & Services Co., Ltd.Inventors: Yusaku Otsuka, Naoya Mashiko, Shin Kokura, Yu Iwasaki, Ryuichi Murakawa, Akira Bando, Wataru Sasaki, Hideyuki Yoshikawa, Masamitsu Kobayashi
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Publication number: 20110302393Abstract: When executing sequential processing such as a ladder logic, converting a program formed of an instruction set of another processor to a program executable by an own processor in software and then conducting processing lowers the real time property. In a control system, a storage unit stores a program for the own processor and a program for another processor. A processor reads data from the storage unit, executes processing described as a program, and gives an instruction to change over a method for acquiring data from the storage unit, to a conversion instruction unit according to data contents. A changeover unit is connected to the storage unit directly or via the conversion unit to change over the data acquiring method according to an instruction from the conversion instruction unit. The conversion unit converts data read from the storage unit to data executable by the processor, according to a conversion scheme.Type: ApplicationFiled: June 6, 2011Publication date: December 8, 2011Inventors: Noritaka Matsumoto, Tsutomu Yamada, Akihiro Ohashi, Shin Kokura
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Publication number: 20110214125Abstract: An input/output control apparatus including: a unit that controls input/output of data relating to a computation of a plurality of processors in response to an access request from a second input/output unit and an access request from a first input/output unit which requires higher reliability than said second input/output unit, and orders at least one of a plurality of processors to perform a computation relating to the access request from said first input/output unit away from the computation relating to the access request from said second input/output unit in case of that said first input/output unit issued an access request, so that a same computation is made by said plurality of processors; a unit that compares the results of said computations relative to the access request from said first input/output unit provided from said plurality of processors; and a unit that allows the data associated with said computations of said processors to be output on the basis of said compared results.Type: ApplicationFiled: May 11, 2011Publication date: September 1, 2011Inventors: Akira Bando, Shin Kokura, Takashi Umehara, Masamitsu Kobayashi, Hisao Nagayama, Naoya Mashiko, Masakazu Ishikawa, Masahiro Shiraishi, Akihiro Onozuka, Hiromichi Endoh, Tsutomu Yamada, Satoru Funaki
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Publication number: 20110113277Abstract: A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.Type: ApplicationFiled: November 3, 2010Publication date: May 12, 2011Inventors: Noritaka Matsumoto, Tsutomu Yamada, Eiji Kobayashi, Akihiro Ohashi, Shin Kokura
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Publication number: 20110022936Abstract: A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections.Type: ApplicationFiled: October 8, 2010Publication date: January 27, 2011Inventors: Akihiro ONOZUKA, Masakazu Ishikawa, Masamitsu Kobayashi, Takashi Umehara, Shin Kokura, Hiromichi Endoh, Satoru Funaki, Hisao Nagayama, Masahiro Shiraishi, Akira Bando, Eiji Kobayashi, Yasuyuki Furuta, Naoya Mashiko
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Patent number: 7873871Abstract: A programmable electronic controller in which one central arithmetic processing unit and a plurality of input devices and output devices are connected by means of a parallel bus, the controller being basically configured to activate a self-diagnostic function and a diagnostic test of the input devices and the output devices with an instruction from a microprocessor of the central arithmetic processing unit; and to judge the result with the microprocessor of the central arithmetic processing unit, by using the microprocessor installed in the central arithmetic processing unit also as a processor for tests (diagnostic tests) of the self-diagnostic function of the input devices and output devices and conducting tests of the self-diagnostic function of the plurality of input devices and output devices with the central arithmetic processing unit.Type: GrantFiled: June 26, 2007Date of Patent: January 18, 2011Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.Inventors: Masakazu Ishikawa, Akira Bandou, Masahiro Shiraishi, Masamitsu Kobayashi, Yasuyuki Furuta, Akihiro Onozuka, Shin Kokura, Eiji Kobayashi, Satoru Funaki, Takashi Umehara, Naoya Mashiko, Yuusuke Seki, Tatsuyuki Ootani
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Publication number: 20100174967Abstract: A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection.Type: ApplicationFiled: January 6, 2010Publication date: July 8, 2010Inventors: Satoru Funaki, Yasuhiro Kiyofuji, Masashi Suenaga, Shin Kokura, Eiji Kobayashi, Akihiro Onozuka, Yusuke Seki, Toshiki Shimizu, Yukiko Tahara, Yuta Sugimoto
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Publication number: 20100050062Abstract: The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag.Type: ApplicationFiled: October 29, 2009Publication date: February 25, 2010Inventors: Akihiro ONOZUKA, Masakazu ISHIKAWA, Masamitsu KOBAYASHI, Takashi UMEHARA, Shin KOKURA, Hiromichi ENDOH, Satoru FUNAKI, Hisao NAGAYAMA, Masahiro SHIRAISHI, Akira BANDO, Eiji KOBAYASHI, Yasuyuki FURUTA, Naoya MASHIKO
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Publication number: 20090319756Abstract: The present invention provides a duplexed operation processor control system that includes operation processors, an I/O device, and at least one communication path that couples the operation processors to the I/O device, and at least one communication path that couples the operation processors with each other. The duplexed operation processor control system switches over either of the operation processors to be a primary operation processor that executes a control operation for a control target, and the other to be a secondary operation processor that is in a stand-by state, and the secondary operation processor snoops control data synchronously when the primary operation processor acquires the control data from the control target.Type: ApplicationFiled: June 18, 2009Publication date: December 24, 2009Inventors: Toshiki Shimizu, Akira Bando, Yusaku Otsuka, Yasuhiro Kiyofuji, Elji Kobayashi, Akihiro Onozuka, Satoru Funaki, Masakazu Ishikawa, Hideaki Masuko, Yusuke Seki, Wataru Sasaki, Naoya Mashiko, Akihiro Nakano, Shin Kokura, Shoichi Ozawa, Yu Iwasaki
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Publication number: 20090187261Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.Type: ApplicationFiled: January 23, 2009Publication date: July 23, 2009Inventors: Yusaku Otsuka, Naoya Mashiko, Shin Kokura, Yu Iwasaki, Ryuichi Murakawa, Akira Bando, Wataru Sasaki, Hideyuki Yoshikawa, Masamitsu Kobayashi
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Patent number: 7555627Abstract: Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.Type: GrantFiled: June 30, 2006Date of Patent: June 30, 2009Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.Inventors: Naoya Mashiko, Takashi Umehara, Masamitsu Kobayashi, Hiromichi Endoh, Akihiro Onozuka, Akira Bando, Shin Kokura, Hisao Nagayama, Masakazu Ishikawa, Satoru Funaki, Masahiro Shiraishi
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Publication number: 20080046603Abstract: A control device diagnoses the operation of a bus arbiter that mediates bus usage requests output by multiple devices in the control device to satisfy both responsiveness and safety. A diagnostic module, implemented as an external diagnostic module, monitors signals related to the arbiter mediation and, if an abnormality caused by a signal sticking condition or an abnormality in a mediation control unit is detected, stops data transfer safely to prevent safety data from being output incorrectly.Type: ApplicationFiled: June 28, 2007Publication date: February 21, 2008Inventors: Eiji Kobayashi, Akira Bandou, Masamitsu Kobayashi, Masahiro Shiraishi, Akihiro Onozuka, Takashi Umehara, Shin Kokura, Masakazu Ishikawa, Yasuyuki Furuta, Satoru Funaki, Yuusuke Seki, Tatsuyuki Ootani, Teruaki Sakata, Kotaro Shimamura