Abstract: A method includes forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction, and forming a second portion of the layer on the first portion of the layer by flowing the reactant gas past the substrate in a second direction different from the first direction.

Abstract: An indoor unit included in an air conditioner that includes an outdoor unit includes a power receiving circuit (PR2), a low-frequency transmission and reception circuit as a first reception circuit, a high-frequency transmission and reception circuit as a transmission and reception circuit, and an inner-controller. The low-frequency transmission and reception circuit receives a current signal transmitted from an outdoor unit by using a current loop formed by a power line included in power supply wiring. For a first communication state in which physical connection between with the outdoor unit is recognized and a second communication state in which communication for operation of the air conditioner is performed between with the outdoor unit, the inner-controller selects use of the low-frequency transmission and reception circuit and the high-frequency transmission and reception circuit in the first communication state and the second communication state.

Abstract: A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures, source-level material layers, and a three-dimensional memory array including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film. A vertically alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. A through-memory-level interconnection via structure vertically extends through each plate within the vertically alternating sequence and contacts a center portion of a top surface of one of the lower-level metal interconnect structures.

Abstract: A technology for writing information that varies by object into electronic tags. An electronic tag writing system that includes a writing device that writes writing information into electronic tags; and an information acquisition part that reads writing information and a processing order out of a storage part that stores the processing order in association with writing information for objects that are associated with the electronic tags. The writing information that is associated with the processing order acquired by the information acquisition part is written into the electronic tags by the writing device in accordance with the processing order.

Abstract: A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures, source-level material layers, and a three-dimensional memory array including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film. A vertically alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. A through-memory-level interconnection via structure vertically extends through each plate within the vertically alternating sequence and contacts a center portion of a top surface of one of the lower-level metal interconnect structures.

Abstract: A technology is for writing different information depending on an object into an electronic tag. The above problem is solved by an electronic tag writing system including a writing device that writes write information into an electronic tag, and an information acquisition section that acquires write information related to an object associated with the electronic tag, in which the write information acquired by the information acquisition section is written into the electronic tag using the writing device.

Abstract: A technology is for writing different information depending on an object into an electronic tag. The above problem is solved by an electronic tag writing system including a writing device that writes write information into an electronic tag, and an information acquisition section that acquires write information related to an object associated with the electronic tag, in which the write information acquired by the information acquisition section is written into the electronic tag using the writing device.

Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.

Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.

Abstract: A method of forming a semiconductor device includes forming a dummy metal gate layer including work function metals directly on a base insulator, diffusing the work function metals into the base insulator by annealing, removing the dummy metal gate layer by a wet etching, forming a metal gate on the base insulator, and forming a high-k insulator on the metal gate.

Abstract: A method of forming a semiconductor device includes forming a dummy metal gate layer including work function metals directly on a base insulator, diffusing the work function metals into the base insulator by annealing, removing the dummy metal gate layer by a wet etching, forming a metal gate on the base insulator, and forming a high-k insulator on the metal gate.

Abstract: An increased area of an element transistor to be evaluated causes an increased leakage current due to a tunnel effect, leading to a reduced accuracy in predicting a TDDB lifetime. A test element group (TEG) 1 is a pattern for evaluating electric characteristics, comprising a plurality of unit transistors T11, T12, T13, T21, T22, T23, T31, T32, T33, which are arranged so as to form a lattice-shaped pattern. Each of the unit transistors comprises a gate dielectric serving as an object to be evaluated, and source region and drain region, which are a short-circuited.

Abstract: A metal oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end portion located on each side of the central portion, the end portion being thicker than the central portion and formed of an oxide insulating film. The MOS transistor also includes a p-type gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate insulating film and the gate electrode, a pair of p-type source/drain areas formed in surface portions of the silicon substrate, and a channel area located between the pair of source/drain areas.

Abstract: A MOS transistor of the present invention comprises a gate insulating film disposed on the surface of a silicon substrate, a p-type gate electrode formed on the gate insulating film, and sidewalls formed on both sides of the gate insulating film and the gate electrode. A pair of p-type source/drain areas is provided in surface portions of the silicon substrate, and a channel area is located between the source/drain areas. The gate insulating film comprises a central portion and both end portions located on both sides of the central portion. The central portion is formed of a nitride insulating film containing at least nitrogen, and both end portions are each formed of an oxide insulating film containing oxygen and no nitrogen. The source/drain areas comprise lightly doped source/drain areas located on inner sides in contact with the channel area and deeply doped source/drain areas located on the outer sides of the lightly doped source/drain areas to form an LDD structure.

Abstract: A Metal Oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end portion located on each side of the central portion, the end portion being thicker than the central portion and formed of an oxide insulating film. The MOS transistor also includes a p-type gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate insulating film and the gate electrode, a pair of p-type source/drain areas formed in surface portions of the silicon substrate, and a channel area located between the pair of source/drain areas.

Abstract: A semiconductor apparatus for increasing operating current is provided. The semiconductor apparatus is composed of a P-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) including a first gate insulator which contains first positive charges therein, and an N-channel MISFET including a second gate insulator which contains second positive charges therein. A first charge density of the first positive charge is larger than a second charge density of the second positive charge.

Abstract: A MOS transistor of the present invention comprises a gate insulating film disposed on the surface of a silicon substrate, a p-type gate electrode formed on the gate insulating film, and sidewalls formed on both sides of the gate insulating film and the gate electrode. A pair of p-type source/drain areas is provided in surface portions of the silicon substrate, and a channel area is located between the source/drain areas. The gate insulating film comprises a central portion and both end portions located on both sides of the central portion. The central portion is formed of a nitride insulating film containing at least nitrogen, and both end portions are each formed of an oxide insulating film containing oxygen and no nitrogen. The source/drain areas comprise lightly doped source/drain areas located on inner sides in contact with the channel area and deeply doped source/drain areas located on the outer sides of the lightly doped source/drain areas to form an LDD structure.

Abstract: The semiconductor device fabrication method of the present invention comprises an impurity introduction step of introducing an impurity capable of accelerating thermal oxidation selectively into a first region of the surface of a silicon substrate and an oxidation step of successively carrying out oxidation and oxynitridation for said first region and a second region where no impurity is introduced and forming insulating films with respectively different film thicknesses on the surface of said first region and the surface of said second region.