Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a first lower insulating layer disposed on the cell region and extending onto the peripheral region, a second lower insulating layer disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the peripheral region, data storage patterns disposed on the second lower insulating layer on the cell region, a cell insulating layer disposed on the second lower insulating layer on the cell region and covering the data storage patterns, and a peripheral insulating layer disposed on the second lower insulating layer on the peripheral region and including a material different from the cell insulating layer. A thickness of the second lower insulating layer on the peripheral region is smaller than a maximum thickness of the second lower insulating layer on the cell region.

Abstract: A superconducting device includes a frequency-tunable device including a first conductive pad and a second conductive pad which are connected to each other by a Josephson junction, a ferromagnet having a magnetic domain wall, and a control circuit configured to apply a current to the ferromagnet to adjust a position of the magnetic domain wall of the ferromagnet, and to control a resonance frequency of the frequency-tunable device.

Abstract: A superconducting device includes a frequency tunable device comprising a first conductive pad and a second conductive pad that are connected to each other by a Josephson junction, a ferromagnetic structure disposed at a predetermined distance apart from the first and second conductive pads, a control line located below the ferromagnetic structure, and a control circuit configured to control a resonant frequency of the frequency tunable device by controlling current flowing through the control line.

Abstract: An ultrasonic inspection system includes an ultrasonic scanning station, a support structure and two or more object holders coupled to the support structure. The support structure is moveable between first and second orientations. The object holders enable an object to be held for ultrasonic scanning. In the first orientation of the support structure, a first object holder is to be held in an ultrasonic scanning station and a second object holder is positioned to allow loading or unloading. In the second orientation, the second object holder is positioned in the ultrasonic scanning station and the first object holder is positioned to allow loading or unloading. The object holders may be raised above a water level for loading/unloading and lowered below the water level for ultrasonic inspection. The object holders may have wafer raisers to hold a semiconductor wafer above the object holder for automated handling.

Abstract: Systems, methods and apparatus related to pre-wetting an edge portion of a bonded wafer prior to wetting a flat, horizontal portion of the bonded wafer. The apparatus includes a frame having nozzles directed such that couplant discharged from these nozzles wet the edge of the wafer. The edge nozzles have couplant flow vectors that interface to dampen the trajectory of fluid to reduce splash and pre-wet the edges of the bonded wafer.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.

Abstract: The present inventors have arrived at the present application by confirming that a novel quinazolinone derivative exhibits therapeutic efficacy for metabolic disorders. The quinazolinone derivative according to the present application has a similar structure to that of idelalisib, but exhibits very different properties and a different mechanism of action from idelalisib. In addition, this derivative molecule was shown to have excellent efficacy against metabolic disorders, in particular lipid metabolic disorders, through different mechanism of action. The derivative molecule also showed excellent efficacy against non-alcoholic steatohepatitis (NASH). No non-alcoholic steatohepatitis treatment drugs have been approved at the time of filing.

Abstract: A semiconductor device includes a substrate including a first region and a second region, data storage patterns on the first region and spaced apart from each other in a first direction, an upper insulating layer on the first and second regions and on the data storage patterns , a cell line structure penetrating the upper insulating layer on the first region, extending in the first direction, and electrically connected to the data storage patterns, and an upper connection structure penetrating the upper insulating layer on the second region. The upper connection structure includes an upper conductive line, and upper conductive contacts arranged along a bottom surface of the upper conductive line. The bottom surface of the upper conductive line is located at a height higher than a bottom surface of the cell line structure. A side surface of the cell line structure has a straight line shape continuously-extended.

Abstract: A coupler and a chuck are described. The chuck is configured to secure an article while the wafer is undergoing an inspection process. The chuck has a plurality of vacuum areas. Some vacuum areas hold the wafer in place while other vacuum areas suction couplant from the edge surface of the wafer. The coupler is used to inspect a surface and subsurface of the wafer for defects and includes a sensing device, which may be a transducer. One or more couplant inlet couplings are disposed on a second portion of the coupler, the couplant inlet couplings provide a couplant to a portion of the wafer inspected by the sensing device. A plurality of vacuum inlet couplings is disposed on a third portion of the coupler. At least one of the vacuum inlet couplings provide suction through a recessed portion of a lower surface of the coupler to remove couplant that is outside the portion of the wafer that is being inspected by the sensing device.

Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.

Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.

Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.

Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.

Abstract: A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.

Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.

Abstract: In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures.

Abstract: A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.

Abstract: In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures.