Abstract: The multimedia processing system includes a plurality of first units including a CPU and a top domain; a storage domain configured to store a plurality of multimedia data; a multimedia codec domain configured to decode segments of target multimedia data received from the storage domain and to output decoded segments according to control of the CPU or the top domain; a system bus configured to connect the plurality of first units, the storage domain, and the multimedia codec domain with one another; and an alive domain configured to control power supply to the plurality of first units, the storage domain, the multimedia codec domain, and the system bus and to receive a signal from a user.

Abstract: The multimedia processing system includes a plurality of first units including a CPU and a top domain; a storage domain configured to store a plurality of multimedia data; a multimedia codec domain configured to decode segments of target multimedia data received from the storage domain and to output decoded segments according to control of the CPU or the top domain; a system bus configured to connect the plurality of first units, the storage domain, and the multimedia codec domain with one another; and an alive domain configured to control power supply to the plurality of first units, the storage domain, the multimedia codec domain, and the system bus and to receive a signal from a user.

Abstract: The multimedia processing system includes a plurality of first units including a CPU and a top domain; a storage domain configured to store a plurality of multimedia data; a multimedia codec domain configured to decode segments of target multimedia data received from the storage domain and to output decoded segments according to control of the CPU or the top domain; a system bus configured to connect the plurality of first units, the storage domain, and the multimedia codec domain with one another; and an alive domain configured to control power supply to the plurality of first units, the storage domain, the multimedia codec domain, and the system bus and to receive a signal from a user.

Abstract: The multimedia processing system includes a plurality of first units including a CPU and a top domain; a storage domain configured to store a plurality of multimedia data; a multimedia codec domain configured to decode segments of target multimedia data received from the storage domain and to output decoded segments according to control of the CPU or the top domain; a system bus configured to connect the plurality of first units, the storage domain, and the multimedia codec domain with one another; and an alive domain configured to control power supply to the plurality of first units, the storage domain, the multimedia codec domain, and the system bus and to receive a signal from a user.

Abstract: A method of heating an integrated circuit (IC) may include sensing a temperature of the IC, comparing the sensed temperature with a reference temperature and generating a comparison signal; and enabling a heating element that heats the IC based on the comparison signal. An IC may include a thermal sensor configured to sense a temperature of the IC, compare the sensed temperature with a reference temperature, and generate a comparison signal. The IC may include a heating element configured to be enabled to heat the IC based on the comparison signal. An IC may include a heating element and a thermal sensor. The sensor may be configured to sense a temperature of the IC and generate a control signal based on the sensed temperature and a reference temperature. The element may be enabled to heat the IC or disabled from heating the IC based on the control signal.

Abstract: A method and apparatus for booting a microprocessor system using a serial (e.g., NAND-type) flash memory array having a random-access (parallel, e.g., NOR-flash type) interface. The method includes loading a boot code loader stored in the serial (e.g., NAND-type) flash memory array into a RAM when power is turned on, according to a routine of a read-only memory (ROM) of the microprocessor; loading boot code stored in the serial flash memory into an internal or external (main) RAM of the microprocessor according to the boot code loader; loading application code stored in the serial flash memory into the main (RAM) memory according to the boot code; and executing the application code. The system may be manufactured at a low cost compared to NOR-Flash based systems, while ensuring flexibility of a microprocessor.

Abstract: Disclosed is a method for managing a DSS (Digital Slow Shutter) mode in a monitoring camera. When an iris of the monitoring camera is maximally opened and a shutter speed is minimum, the DSS mode is set. In the DSS mode, a video frame inputted in a predetermined cycle is stored in a memory. A plurality of video frames stored in the memory are synthesized into a monitoring video frame. The monitoring video frame is outputted irrespective of a luminance thereof. When the memory is full of the video frames, an oldest stored video frame is replaced with a newly inputted video frame. The monitoring video frame can be consecutively outputted in a predetermined cycle even though the monitoring camera operates in the DSS mode. The monitoring video frame based on a bright luminance level can be outputted, such that a monitoring function is enhanced.

Abstract: A method and apparatus for booting a microprocessor system using a serial (e.g., NAND-type) flash memory array having a random-access (parallel, e.g., NOR-flash type) interface. The method includes loading a boot code loader stored in the serial (e.g., NAND-type) flash memory array into a RAM when power is turned on, according to a routine of a read-only memory (ROM) of the microprocessor; loading boot code stored in the serial flash memory into an internal or external (main) RAM of the microprocessor according to the boot code loader; loading application code stored in the serial flash memory into the main (RAM) memory according to the boot is code; and executing the application code. The system may be manufactured at a low cost compared to NOR-Flash based systems, while ensuring flexibility of a microprocessor.

Abstract: A pickup inspection apparatus has a machine unit, spindle and feed motors, a servo unit, a position detection unit, a measurement unit and a control unit. In the machine unit, a pickup module to be inspected and a test disc for inspection are installed. The spindle motor is installed in the machine unit to rotate the test disc. The feed motor is installed in the machine unit to perform a tracking operation. The servo unit drives the spindle and the feed motors. The position detection unit detects a tracking position by the feed motor. The measurement unit processes signals outputted from the pickup module. The control unit controls the servo unit and the measurement unit and determines the state of the pickup module according to a measurement result of the measurement unit.