Patents by Inventor Shin-Luh Tarng

Shin-Luh Tarng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164756
    Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Xu Lu, Tang-Yuan Chen, Jin-Yuan Lai, Tse-Chuan Chou, Meng-Kai Shih, Shin-Luh Tarng
  • Publication number: 20210327815
    Abstract: A substrate, a semiconductor package device and a method of manufacturing a semiconductor device package are provided. The substrate includes a low density wiring structure, a first middle density wiring structure and high density wiring structure. The first middle density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure and the first middle density wiring structure are disposed side by side. A line space of a circuit layer of the low density wiring structure is greater than a line space of a circuit layer of the first middle density wiring structure. The line space of the circuit layer of the first middle density wiring structure is greater than a line space of a circuit layer of the high density wiring structure.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ian HU, Shin-Luh TARNG
  • Publication number: 20210288024
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
  • Publication number: 20210202349
    Abstract: A semiconductor device package includes a semiconductor die and an anisotropic thermal conductive structure. The semiconductor die includes a first surface, a second surface opposite to the first surface and edges connecting the first surface to the second surface. The anisotropic thermal conductive structure has different thermal conductivities in different directions. The anisotropic thermal conductive structure includes at least two pairs of film stacks, and each pair of the film stacks comprises a metal film and a nano-structural film alternately stacked. The anisotropic thermal conductive structure comprises a first thermal conductive section disposed on the first surface of the semiconductor die, and the first thermal conductive section is wider than the semiconductor die.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-En CHEN, Hung-Hsien HUANG, Shin-Luh TARNG
  • Patent number: 11011496
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 18, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
  • Publication number: 20210074676
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
  • Patent number: 10872861
    Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC. KAOHSIUNG, TAIWAN
    Inventors: Yong-Da Chiu, Shiu-Chih Wang, Shang-Kun Huang, Ying-Ta Chiu, Shin-Luh Tarng, Chih-Pin Hung
  • Patent number: 10861726
    Abstract: An apparatus includes: a first image capture module, a second image capture module, and a first projector. The first image capture module has a first optical axis forming an angle from approximately 70° to approximately 87° with respect to the surface of a carrier. The second image capture module has a first optical axis forming an angle of approximately 90° with respect to the surface of the carrier. The first projector has a first optical axis forming an angle from approximately 40° to approximately 85° with respect to the surface of the carrier.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 8, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun Hung Tsai, Hsuan Yu Chen, Ian Hu, Meng-Kai Shih, Shin-Luh Tarng
  • Publication number: 20200211863
    Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ying-Xu LU, Tang-Yuan CHEN, Jin-Yuan LAI, Tse-Chuan CHOU, Meng-Kai SHIH, Shin-Luh TARNG
  • Publication number: 20200098605
    Abstract: An apparatus includes: a first image capture module, a second image capture module, and a first projector. The first image capture module has a first optical axis forming an angle from approximately 70° to approximately 87° with respect to the surface of a carrier. The second image capture module has a first optical axis forming an angle of approximately 90° with respect to the surface of the carrier. The first projector has a first optical axis forming an angle from approximately 40° to approximately 85° with respect to the surface of the carrier.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun Hung TSAI, Hsuan Yu CHEN, Ian HU, Meng-Kai SHIH, Shin-Luh TARNG
  • Patent number: 10586716
    Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: March 10, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Xu Lu, Tang-Yuan Chen, Jin-Yuan Lai, Tse-Chuan Chou, Meng-Kai Shih, Shin-Luh Tarng
  • Publication number: 20190244909
    Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yong-Da CHIU, Shiu-Chih WANG, Shang-Kun HUANG, Ying-Ta CHIU, Shin-Luh TARNG, Chih-Pin HUNG
  • Publication number: 20190127573
    Abstract: A polylactic acid resin composition includes about 100 parts by weight of a polylactic acid resin, about 0.001 to about 3 parts by weight of a nucleating agent and about 3 to about 70 parts by weight of a filler. The polylactic acid resin composition can be processed into a biodegradable molded article or other product having a high impact strength and a high heat deflection temperature.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 2, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chean-Cheng SU, Chih-Pin HUNG, Shin-Luh TARNG, Chaung Chi WANG, Chao Ming TSENG, Shiu-Chih WANG
  • Patent number: 8431007
    Abstract: An electro-thinning apparatus for removing excess metal from the surface metal layer of the substrate is provided. The apparatus includes an electrolysis bath, a transportation system, an anode roller, a cathode roller, and at least one shielding plate. The electrolysis bath contains an electrolysis liquid. The transportation system is disposed in the electrolysis bath for moving a substrate from an upstream end to a downstream end. The anode roller is disposed relative to the electrolysis bath and located upstream to the transportation system. The cathode roller is located above the transportation system and located downstream to the anode roller. The at least one shielding plate is located downstream to the cathode roller. During electrolysis, the anode roller contacts a surface metal layer of the substrate while the cathode roller is partly immersed in the electrolysis liquid and away from the surface metal layer of the substrate during electrolysis.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: April 30, 2013
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Shin-Luh Tarng, Chao-Fu Weng
  • Publication number: 20100239857
    Abstract: A method of manufacturing an embedded-trace substrate is provided. A core plate, which comprises a central core, a first and a second thick resin layers respectively formed on top and bottom sides of the central core, is provided. Next, a through hole and a plurality of trenches are formed on the core plate, wherein the through hole passes through the core plate, and the trenches are formed on the upper and the lower surfaces of the core plate. Then, the core plate is subjected to one-plating step for electroplating a conductive material in the through hole and the trenches at the same time. Afterwards, the excess conductive material is removed from the upper and lower surfaces of the core plate so that the surfaces of the conductive material filling in the through hole and the trenches are coplanar with the surfaces of the first and second thick resin layers.
    Type: Application
    Filed: December 28, 2009
    Publication date: September 23, 2010
    Inventors: Shin-Luh Tarng, Teck-Chong Lee