Patents by Inventor Shin Matsuda

Shin Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220283012
    Abstract: A rapid rise in the temperature of a liquid level sensor is prevented even at close to a vacuum atmosphere. In a material supply system that is equipped with a tank containing a liquid material and with the liquid level sensor that is provided inside the tank, and in which the liquid level sensor is a self-heating type of sensor that, when the liquid level sensor is generating heat as a result of being supplied with a predetermined normal energy, detects a liquid surface, there are provided a monitoring portion that monitors a detection value from an output signal from the liquid level sensor, and an energy control portion that, when the monitored detection value reaches a predetermined upper limit value, performs control in such a way that the energy supplied to the liquid level sensor is low-level energy that is lower than the normal energy.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 8, 2022
    Inventors: Akihiro TAGUCHI, Kensuke TSUJI, Yuki MIZUYAMA, Akihiro NAKAMURA, Shin MATSUDA
  • Patent number: 11174527
    Abstract: A heat-treatment apparatus includes a casing, a loader which loads a workpiece to an inner part of the casing in order to apply a heat-treatment to the workpiece, and a canopy surface provided in the casing to cover the workpiece. The canopy surface includes a slope way with a sectional configuration where the canopy surface is cut on a plane vertical to a conveying direction of the workpiece inside the casing. The slope way includes a highest point and a downward inclined surface extending from the highest point to an outside of a zone between a perpendicular line extending from a left end of the workpiece and a perpendicular line extending from a right end of the workpiece.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: November 16, 2021
    Assignees: MITSUI HIGH-TEC, INC., KOYO THERMO SYSTEMS CO., LTD.
    Inventors: Takeaki Kozono, Yusuke Hasuo, Showa Tachisato, Shin Matsuda
  • Publication number: 20160258034
    Abstract: A heat-treatment apparatus includes a casing, a loader which loads a workpiece to an inner part of the casing in order to apply a heat-treatment to the workpiece, and a canopy surface provided in the casing to cover the workpiece. The canopy surface includes a slope way with a sectional configuration where the canopy surface is cut on a plane vertical to a conveying direction of the workpiece inside the casing. The slope way includes a highest point and a downward inclined surface extending from the highest point to an outside of a zone between a perpendicular line extending from a left end of the workpiece and a perpendicular line extending from a right end of the workpiece.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 8, 2016
    Applicants: MITSUI HIGH-TEC , INC., KOYO THERMO SYSTEMS CO., LTD.
    Inventors: Takeaki KOZONO, Yusuke HASUO, Showa TACHISATO, Shin MATSUDA
  • Publication number: 20050079098
    Abstract: A microchemical chip includes a base having a channel for causing fluids to-be-treated to flow therethrough, and supply portions connected to the channel, for causing the fluids to-be-treated to flow into the channel, respectively. In the microchemical chip, a plurality of fluids to-be-treated are respectively caused to flow from the supply portions into the channel, and the plurality of fluids to-be-treated caused to flow in are merged to be subjected to chemical reactions. In the microchemical chip, heaters are formed for heating the fluid to-be-treated flowing through supply channels of the supply portions.
    Type: Application
    Filed: June 24, 2004
    Publication date: April 14, 2005
    Inventors: Shin Matsuda, Kuninori Yokomine, Katsuhiko Onitsuka, Masanao Kabumoto
  • Publication number: 20040265184
    Abstract: A substrate provided with a channel through which a fluid to be treated flows is formed by forming a groove portion by pressing a surface of a ceramic green sheet with a pattern having a predetermined shape, laminating another ceramic green sheet on the surface of the ceramic green sheet in which the groove portion is formed in such a manner that the groove portion is covered, and sintering the laminated ceramic green sheets at a predetermined temperature, so that a microchemical chip is obtained. The microchemical chip is provided with a structure for generating a turbulent flow in the fluid to be treated flowing through the channel.
    Type: Application
    Filed: April 15, 2004
    Publication date: December 30, 2004
    Applicant: KYOCERA CORPORATION
    Inventors: Shin Matsuda, Kuninori Yokomine
  • Publication number: 20040265992
    Abstract: A microchemical chip includes a base including a channel for causing a fluid to-be-treated to flow therethrough, supply portions connected to the channel, for causing the fluids to-be-treated to flow therefrom into the channel, respectively, and a collection portion from which a fluid in the channel is drawn to the outside. A plurality of fluids to-be-treated are respectively caused to flow from the supply portions into the channel, and the plurality of fluids to-be-treated caused to flow in are merged and subjected to a predetermined treatment, and then the treated fluid is drawn from the collection portion to the outside. In this microchemical chip, the base is formed by attaching a base body made of ceramics and a lid made of glass, and electrodes that are used for capillary migration are formed by being sintered simultaneously with the base body.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 30, 2004
    Applicant: KYOCERA CORPORATION
    Inventors: Shin Matsuda, Katsuhiko Onitsuka
  • Patent number: 6614183
    Abstract: A plasma display panel includes a plurality of row electrode pairs (X, Y) forming display lines which are formed on a front glass substrate (10). Each row electrode (X, Y) of the row electrode pair (X, Y) makes up transparent electrodes (Xa, Ya) each formed opposing the corresponding transparent electrode (Xa, Ya) via a discharge gap (g) for each pair, and a bus electrode (Xb, Yb) connected to the transparent electrodes (Xa, Ya). In such plasma display panel, a light-shield layer 20A is formed at least on a portion between the two bus electrodes situated back to back and a required portion in proximal to sides of the bus electrodes (Xb, Yb) connected to the transparent electrodes (Xa, Ya) on the front glass substrate (10).
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: September 2, 2003
    Assignee: Pioneer Corporation
    Inventors: Kohsuke Masuda, Hitoshi Taniguchi, Toshihiro Komaki, Kimio Amemiya, Sota Okamoto, Shin Matsuda, Hiroshi Adachihara
  • Publication number: 20010017520
    Abstract: A plasma display panel includes a plurality of row electrode pairs (X, Y) forming display lines which are formed on a front glass substrate (10). Each row electrode (X, Y) of the row electrode pair (X, Y) makes up transparent electrodes (Xa, Ya) each formed opposing the corresponding transparent electrode (Xa, Ya) via a discharge gap (g) for each pair, and a bus electrode (Xb, Yb) connected to the transparent electrodes (Xa, Ya). In such plasma display panel, a light-shield layer 20A is formed at least on a portion between the two bus electrodes situated back to back and a required portion in proximal to sides of the bus electrodes (Xb, Yb)connected to the transparent electrodes (Xa, Ya) on the front glass substrate (10).
    Type: Application
    Filed: February 5, 2001
    Publication date: August 30, 2001
    Applicant: Pioneer Corporation
    Inventors: Kohsuke Masuda, Hitoshi Taniguchi, Toshihiro Komaki, Kimio Amemiya, Sota Okamoto, Shin Matsuda, Hiroshi Adachihara
  • Patent number: 6225700
    Abstract: A package for housing a semiconductor element includes a substrate of electrically insulating material and having a semiconductor element-mounting portion at an upper surface thereof onto which the semiconductor element is mounted. The substrate has a plurality of depression portions at a lower surface thereof, and a plurality of metallized wiring layers lead out from the periphery of the semiconductor element-mounting portion and extend to the bottom surfaces of the depression portions. A plurality of connection pads formed on the bottom surfaces of the depression portions are electrically connected to the metallized wiring layers. Terminals which are attached to the connection pads each have a ball-like protruding portion at the lower surface of the insulating substrate and comprise non-eutectic solder. The package may be provided with metallic pads formed on the lower surface of the insulating substrate, and metallic balls attached to the metallic pads.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: May 1, 2001
    Assignee: Kyocera Corporation
    Inventors: Nobuyuki Ito, Shin Matsuda
  • Patent number: 5918796
    Abstract: A method of fabricating a package for housing a semiconductor element, comprising applying solder paste within plural depressions which are formed on at least one principal surface of an insulating substrate and have electrical connection pads, protruding the surface of the solder paste from the principal surface of the insulating substrate, mounting solder balls on the surface of the solder paste, and fusing the solder paste and the solder balls to produce unitary structures in order to form connection terminals with spherical protrusions.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: July 6, 1999
    Assignee: Kyocera Corporation
    Inventors: Shin Matsuda, Shingo Sato
  • Patent number: 5512786
    Abstract: A package for housing semiconductor elements including an insulating base which consists of electrical insulation material, and has a mounting portion that mounts semiconductor elements on the upper surface as well as a plurality of depressions on either of the upper surface and the lower surface thereof, a plurality of metallized wiring layers led away from the periphery of the mounting portion and extending to one end surface of the depressions, a plurality of connection pads for electrically connecting the metallized wiring layers formed on the end surface of the depressions of the insulating base and terminals which are soldered to the connection pads, wherein the terminals are accurately attached by solder to designated positions on the connection pads and securely and strongly joined to designated wire conductors of external electronic circuit boards to achieve reliable electrical connections of semiconductor integrated circuit elements housed inside the package to external electronic circuit boards.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: April 30, 1996
    Assignee: Kyocera Corporation
    Inventors: Hitomi Imamura, Shin Matsuda, Nobuyuki Ito, Kazuhiro Kawabata