Patents by Inventor Shin Nakao
Shin Nakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6191493Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.Type: GrantFiled: March 2, 1999Date of Patent: February 20, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Shin Nakao, Shinji Baba, Mitsuyasu Matsuo, Hironori Matsushima
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Patent number: 5920770Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.Type: GrantFiled: April 14, 1997Date of Patent: July 6, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Shin Nakao, Shinji Baba, Mitsuyasu Matsuo, Hironori Matsushima
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Patent number: 5753973Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.Type: GrantFiled: February 11, 1997Date of Patent: May 19, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Shin Nakao, Shinji Baba, Mitsuyasu Matsuo, Hironori Matsushima
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Patent number: 5656863Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.Type: GrantFiled: February 17, 1994Date of Patent: August 12, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Yasunaga, Shin Nakao, Shinji Baba, Mitsuyasu Matsuo, Hironori Matsushima
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Patent number: 5366794Abstract: A tape carrier for semiconductor apparatus and a method of manufacturing the tape carrier includes three or more layers and contact holes of small size. A peelable agent is applied to a planar substrate made of glass or the like, and plural insulating layers and plural conductive layers are alternatingly formed thereon in predetermined patterns. The peelable agent is then removed to peel the tape carrier from the substrate. The tape carrier includes the insulating layers and the conductive layers and has projection electrodes but no tape base.Type: GrantFiled: February 13, 1992Date of Patent: November 22, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shin Nakao
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Patent number: 5016084Abstract: A semiconductor device is provided with an electrically conductive cap having a sufficiently thick edge portion for preventing warpage due to the hardening of an encapsulating resin. Since the edge portion of the conductive cap is formed into the shape of a frame, and its thickness is made large, the mechanical strength of the conductive cap is improved, so that even when stress is applied to the conductive cap owing to the hardening of the encapsulating resin, the conductive cap is unlikely to undergo deformation, thereby preventing the warping of the semiconductor device.Type: GrantFiled: April 2, 1990Date of Patent: May 14, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shin Nakao
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Patent number: 4654966Abstract: A heat dissipating member including a heat sink is placed on a module base board with flip-chips mounted thereon, with metallic plates and first adhesive materials of a good thermal conductivity interposed between the heat dissipating member and the flip-chips in a close contact relation and with a second adhesive material interposed between the heat dissipating member and the base board, wherein the first adhesive material is selected to have a melting point lower than that of the second adhesive material, and then such an assembly is heated so that both the first and second adhesive materials are melted and the metallic plates are mounted onto the flip-chips and the heat dissipating member is mounted onto the base board. A gap is formed between the metallic plates and the heat dissipating member as a result of earlier solidification of the second adhesive material than that of the first adhesive material so as to be precisely controlled such that a heat transferring effect therebetween may not be degraded.Type: GrantFiled: October 3, 1985Date of Patent: April 7, 1987Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masanobu Kohara, Shin Nakao, Hiroshi Shibata
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Patent number: 4561011Abstract: A heat dissipating member including a heat sink is placed on a module base board with flip-chips mounted thereon, with metallic plates and first adhesive materials of a good thermal conductivity interposed between the heat dissipating member and the flip-chips in a close contact relation and with a second adhesive material interposed between the heat dissipating member and the base board, wherein the first adhesive material is selected to have a melting point lower than that of the second adhesive material, and then such an assembly is heated so that both the first and second adhesive materials are melted and the metallic plates are mounted onto the flip-chips and the heat dissipating member is mounted onto the base board. A gap is formed between the metallic plates and the heat dissipating member as a result of earlier solidification of the second adhesive material than that of the first adhesive material so as to be precisely controlled such that a heat transferring effect therebetween may not be degraded.Type: GrantFiled: September 22, 1983Date of Patent: December 24, 1985Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masanobu Kohara, Shin Nakao, Hiroshi Shibata