Patents by Inventor Shin Takizawa

Shin Takizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230197845
    Abstract: A semiconductor device includes a cell portion and a peripheral portion. The cell portion has a semiconductor element including a drift layer, a first impurity region, a second impurity region, trench-gate structures, a high-concentration layer, an interlayer insulating film, a first electrode and a second electrode. The interlayer insulating film is located on the trench-gate structures, the first impurity region and the second impurity region, and has a first contact hole communicating with the first impurity region and the second impurity region. The peripheral portion has a section facing the cell portion in one direction, and the interlayer insulating film further has a second contact hole at the section of the peripheral portion. The second contact hole exposes the first impurity region, and the first electrode is electrically connected to the first impurity region through the second contact hole in the peripheral portion.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 22, 2023
    Inventors: SHIN TAKIZAWA, YUSUKE NONAKA, KENTA GOUDA, SHUNSUKE HARADA
  • Patent number: 11476187
    Abstract: On a substrate, a wiring layer is arranged by sequentially stacking a first insulation film, a lower electrode, a second insulation film, an intermediate electrode, a third insulation film, and an upper electrode in this order. A capacitor includes a first capacitor having the lower electrode and the intermediate electrode, and a second capacitor having the intermediate electrode and the upper electrode. The first capacitor and the second capacitor are connected in parallel to each other by electrically connecting the lower electrode and the upper electrode. Further, the intermediate electrode has a higher potential than the lower layer electrode and the upper electrode.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: October 18, 2022
    Assignee: DENSO CORPORATION
    Inventors: Shin Takizawa, Seiji Noma, Yusuke Nonaka, Shinichirou Yanagi, Atsushi Kasahara, Shogo Ikeura
  • Patent number: 11322584
    Abstract: A semiconductor device includes a semiconductor substrate, an upper diffusion region and a lower diffusion region. The semiconductor substrate has a main surface. The upper diffusion region of a first conductivity type is disposed close to the main surface of the semiconductor device. The lower diffusion region of a second conductivity type is disposed up to a position deeper than the upper diffusion region in a depth direction of the semiconductor substrate from the main surface as a reference, and has a higher impurity concentration than the semiconductor substrate. A diode device is provided by having a PN junction surface at an interface between the upper diffusion region and the lower diffusion region, and the PN junction surface has a curved surface disposed at a portion opposite to the main surface.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 3, 2022
    Assignee: DENSO CORPORATION
    Inventors: Shin Takizawa, Yusuke Nonaka, Shinichirou Yanagi, Atsushi Kasahara, Shogo Ikeura
  • Patent number: 11114571
    Abstract: A semiconductor device includes: a semiconductor substrate having a diode formation region; an upper diffusion region of a first conductivity type provided on a surface layer of a main surface of the semiconductor substrate in the diode formation region; and a lower diffusion region of a second conductivity type provided at a position deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, the lower diffusion region having a higher impurity concentration as compared to the semiconductor substrate. The lower diffusion region provides a PN joint surface with the upper diffusion region at a position deeper than the main surface, and has a maximum point indicating a maximum concentration in an impurity concentration profile of the lower diffusion region in the diode formation region.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 7, 2021
    Assignee: DENSO CORPORATION
    Inventors: Shinichirou Yanagi, Yusuke Nonaka, Seiji Noma, Shinya Sakurai, Shogo Ikeura, Atsushi Kasahara, Shin Takizawa
  • Publication number: 20210074631
    Abstract: On a substrate, a wiring layer is arranged by sequentially stacking a first insulation film, a lower electrode, a second insulation film, an intermediate electrode, a third insulation film, and an upper electrode in this order. A capacitor includes a first capacitor having the lower electrode and the intermediate electrode, and a second capacitor having the intermediate electrode and the upper electrode. The first capacitor and the second capacitor are connected in parallel to each other by electrically connecting the lower electrode and the upper electrode. Further, the intermediate electrode has a higher potential than the lower layer electrode and the upper electrode.
    Type: Application
    Filed: October 30, 2020
    Publication date: March 11, 2021
    Inventors: Shin TAKIZAWA, Seiji NOMA, Yusuke NONAKA, Shinichirou YANAGI, Atsushi KASAHARA, Shogo IKEURA
  • Publication number: 20210028277
    Abstract: A semiconductor device includes a semiconductor substrate, an upper diffusion region and a lower diffusion region. The semiconductor substrate has a main surface. The upper diffusion region of a first conductivity type is disposed close to the main surface of the semiconductor device. The lower diffusion region of a second conductivity type is disposed up to a position deeper than the upper diffusion region in a depth direction of the semiconductor substrate from the main surface as a reference, and has a higher impurity concentration than the semiconductor substrate. A diode device is provided by having a PN junction surface at an interface between the upper diffusion region and the lower diffusion region, and the PN junction surface has a curved surface disposed at a portion opposite to the main surface.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Inventors: Shin TAKIZAWA, Yusuke NONAKA, Shinichirou YANAGI, Atsushi KASAHARA, Shogo IKEURA
  • Patent number: 10854543
    Abstract: A semiconductor device includes: a substrate; a first wiring layer arranged above the substrate; a first insulating film covering the first wiring layer; a lower oxidation preventing film arranged on the first insulating film; at least one thin-film resistor arranged on the lower oxidation preventing film; an upper oxidation preventing film arranged on the at least one thin-film resistor; a second insulating film covering the lower oxidation preventing film, the at least one thin-film resistor, and the upper oxidation preventing film; a second wiring layer arranged on the second insulating film; and a third insulating film covering the second wiring layer. The first wiring layer overlaps an end portion of the at least one thin-film resistor when viewed in a normal direction of one surface of the substrate.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: December 1, 2020
    Assignee: DENSO CORPORATION
    Inventors: Shin Takizawa, Takashi Nakano
  • Publication number: 20190229219
    Abstract: A semiconductor device includes: a semiconductor substrate having a diode formation region; an upper diffusion region of a first conductivity type provided on a surface layer of a main surface of the semiconductor substrate in the diode formation region; and a lower diffusion region of a second conductivity type provided at a position deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, the lower diffusion region having a higher impurity concentration as compared to the semiconductor substrate. The lower diffusion region provides a PN joint surface with the upper diffusion region at a position deeper than the main surface, and has a maximum point indicating a maximum concentration in an impurity concentration profile of the lower diffusion region in the diode formation region.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 25, 2019
    Inventors: Shinichirou YANAGI, Yusuke NONAKA, Seiji NOMA, Shinya SAKURAI, Shogo IKEURA, Atsushi KASAHARA, Shin TAKIZAWA
  • Publication number: 20170256505
    Abstract: A semiconductor device includes: a substrate; a first wiring layer arranged above the substrate; a first insulating film covering the first wiring layer; a lower oxidation preventing film arranged on the first insulating film; at least one thin-film resistor arranged on the lower oxidation preventing film; an upper oxidation preventing film arranged on the at least one thin-film resistor; a second insulating film covering the lower oxidation preventing film, the at least one thin-film resistor, and the upper oxidation preventing film; a second wiring layer arranged on the second insulating film; and a third insulating film covering the second wiring layer. The first wiring layer overlaps an end portion of the at least one thin-film resistor when viewed in a normal direction of one surface of the substrate.
    Type: Application
    Filed: October 2, 2015
    Publication date: September 7, 2017
    Inventors: Shin TAKIZAWA, Takashi NAKANO
  • Patent number: 6658078
    Abstract: A MOX nuclear fuel assembly employable either for a thermal neutron reactor employing UO2 as the nuclear fuel and light water as the moderator/coolant or for a thermal neutron reactor employing the MOX fuels as the nuclear fuel and light water as the moderator/coolant is provided with only one kind of MOX nuclear fuel rods each of which has relatively large magnitude of the enrichment grade of the fissionable Pu-s or Pu239 and Pu241, the quantity of the MOX nuclear fuel rods being relatively small.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: December 2, 2003
    Assignee: Tokyo Electric Power Co.
    Inventors: Takafumi Anegawa, Shin Takizawa, Shinya Mizokami
  • Publication number: 20030026380
    Abstract: A MOX nuclear fuel assembly employable either for a thermal neutron reactor employing UO2 as the nuclear fuel and light water as the moderator/coolant or for a thermal neutron reactor employing the MOX fuels as the nuclear fuel and light water as the moderator/coolant is provided with only one kind of MOX nuclear fuel rods each of which has relatively large magnitude of the enrichment grade of the fissionable Pu-s or Pu239 and Pu241, the quantity of the MOX nuclear fuel rods being relatively small.
    Type: Application
    Filed: February 6, 2002
    Publication date: February 6, 2003
    Applicant: TOKYO ELECTRIC POWER CO.
    Inventors: Takafumi Anegawa, Shin Takizawa, Shinya Mizokami