Patents by Inventor Shin-te Yang

Shin-te Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Serial bus clock frequency calibration system and method thereof
    Patent number: 8407508
    Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: March 26, 2013
    Assignee: Genesys Logic, Inc.
    Inventors: Wei-te Lee, Shin-te Yang, Wen-ming Huang
  • Serial bus clock frequency calibration system and method thereof
    Patent number: 8140882
    Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: March 20, 2012
    Assignee: Genesys Logic, Inc.
    Inventors: Wei-te Lee, Shin-te Yang, Yen-fah Chu
  • SERIAL BUS CLOCK FREQUENCY CALIBRATION SYSTEM AND METHOD THEREOF
    Publication number: 20110016346
    Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.
    Type: Application
    Filed: September 16, 2010
    Publication date: January 20, 2011
    Applicant: Genesys Logic, Inc.
    Inventors: Wei-te Lee, Shin-te Yang, Wen-ming Huang
  • SERIAL BUS CLOCK FREQUENCY CALIBRATION SYSTEM AND METHOD THEREOF
    Publication number: 20100122106
    Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.
    Type: Application
    Filed: February 18, 2009
    Publication date: May 13, 2010
    Applicant: GENESYS LOGIC, INC.
    Inventors: Wei-te Lee, Shin-te Yang, Yen-fah Chu