Abstract: MPEG streams of different chroma formats are recorded and reproduced without need to recognize their formats. In an MPEG stream, a header is followed by DCT blocks. Time slots are generated in such a manner that when the chroma format detected from the header is 4:2:2, in all periods of DCT blocks, a process is performed and that when the chroma format detected from the header is 4:2:0, a process is not performed in periods for DCT blocks Cb2 and Cr2 that are not present in the chroma format 4:2:2. The read order of a stream is changed in a memory so as to improve an error resistance. DCT coefficients are rearranged in the order of DC components and AC components from the lowest order component to the highest order component over all DCT blocks. After the stream has been rearranged, time slots are generated in such as manner that when the chroma format is 4:2:0, the process is stopped in the periods for Cb2 and Cr2.

Abstract: A selector has both a function for creating a header of a sequence layer and a header of a picture layer corresponding to reproduced data of a system area and a function for outputting one of an input stream and a stream of which a created header has been added to the header of the input stream as an output stream. When the mode is not high speed reproducing mode, the selector outputs the header contained in the input stream as a header of the output stream. When the mode is high speed reproducing mode, a header (the header of the sequence layer and the header of the picture layer) is created corresponding to data reproduced from the system area. The selector outputs an output stream of which the created header has been added to the input stream.

Abstract: A stream processing apparatus and method for replacing a macroblock having a syntax error in an encoded stream with a macroblock having an acceptable syntax. In such apparatus and method, a plurality of coding parameters may be extracted from the source encoded stream, an error macroblock having a syntax error in the source encoded stream may be detected, the source encoded stream may be variable-length decoded so as to generate a variable-length-decoded stream, a predetermined macroblock having an acceptable syntax may be generated which conforms to a MPEG (motion picture image coding experts group) standard, and the error macroblock of the variable-length decoded stream may be replaced with the predetermined macroblock.

Abstract: A detection circuit detects a slice start code from an input stream. Based on a result of the detection and a frame pulse, a reference macroblock (MB) address generated by a timing generator is sent to an address comparator. The input stream which has been phase-adjusted by a delay circuit is supplied to a variable length decoder (VLD) for decoding a variable length code to detect an MB address. The address comparator compares the reference MB address with the MB address to check the continuity of the MB address. If it is discontinuous, the stream output from the VLD is temporarily interrupted, and a selector selects a replacement data generating circuit in response to a control signal output from the address comparator. The input stream is replaced at a discontinuous macroblock portion with macroblock data which has a correct macroblock address and which is prepared in advance by the replacement data generating circuit.

Abstract: A signal processor provides stable processing, for each frame, of variable-length coded data. An MPEG stream is input in the SDTI format, and a data active length for each frame is determined based on header information for each SDTI frame to generate a “Frame End” signal which is synchronized with the end-of-frame data. The “Frame End” signal is input to a set terminal of an RS flip-flop circuit via a delay circuit. On the other hand, a start code at the beginning of a frame is detected by a detector circuit and an OR circuit, and the result of detection is input to a reset terminal of the RS flip-flop circuit. A switching control is performed so that an enable signal indicates invalid data when the frame end pulse is detected and the enable signal indicates valid data when the start code is detected in response to the output of the RS flip-flop circuit.