Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

Abstract: Embodiments of this application provide a method, an apparatus and a device for measuring a semiconductor structure. Before measurement of a to-be-measured semiconductor structure, a reference semiconductor structure corresponding to the to-be-measured semiconductor structure is set, and a first simulation model corresponding to the to-be-measured semiconductor structure and a second simulation model corresponding to the reference semiconductor structure are established, some structure parameters of the to-be-measured semiconductor structure have parameter values different from those of corresponding structure parameters of the reference semiconductor structure.

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

Abstract: Techniques for performing speech processing using multi-modal widget information are described. A system may receive input data corresponding to a user input. The system may also receive widget context data corresponding to one or more multi-modal widgets active at a device. The system may use the widget context data to perform natural language understanding (NLU) processing with respect to the user input, and for selecting a skill component for responding to the user input. The system may send a widget identifier to the skill component when invoking the skill to respond to the user input.

Abstract: Techniques for performing speech processing using multi-modal widget information are described. A system may receive input data corresponding to a user input. The system may also receive widget context data corresponding to one or more multi-modal widgets active at a device. The system may use the widget context data to perform natural language understanding (NLU) processing with respect to the user input, and for selecting a skill component for responding to the user input. The system may send a widget identifier to the skill component when invoking the skill to respond to the user input.

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a gate structure over the substrate, including a work function layer over the substrate, a dielectric layer at least partially surrounding the gate structure, and a capping layer over the gate structure, wherein a bottom of the capping layer includes at least one protrusion protruding toward the substrate.

Abstract: A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer.

Abstract: Provided is a method for simulating electricity of a wafer chip. The method includes: a database is constructed, the database including spectroscopic data of a semiconductor structure of the wafer chip obtained from a target key process, actual electrical data of the wafer chip, and a correspondence between the spectroscopic data and the actual electrical data; the target key process is performed on a target wafer chip to obtain the spectroscopic data of the semiconductor structure of the target wafer chip obtained from the target key process, the spectroscopic data being target spectroscopic data; the electrical data of the target wafer chip is simulated based on the obtained target spectroscopic data and the database, the electrical data being target electrical data.

Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.

Abstract: A preparation method of the semiconductor structure includes: the substrate including a first area to be etched and a second area to be etched outside the first area to be etched, the etching rate of the first area to be etched and the second area to be etched are different, simultaneously etching the first area to be etched and the second area to be etched at least twice, until an etching depth of one of the first area to be etched and the second area to be etched with a less etching rate is equal to a target etching depth; in at least two etching processes, backfilling a sacrificial material to the first area to be etched and the second area to be etched after a previous etching is completed, removing part of the sacrificial material in a next etching.

Abstract: The embodiments of the present application disclose a contact structure forming method, a contact structure, and a semiconductor device. The method includes: providing a substrate, the substrate having a plurality of isolation regions therein, the isolation regions isolating an active region on the substrate into several portions; etching the active regions and the isolation regions simultaneously by the first etching processing, to form a first contact hole, a protruding active region being formed at the active region in the bottom of the first contact hole; depositing a first dielectric layer to cover the sidewall and bottom of the first contact hole; and etching the bottom of the first contact hole by the second etching processing, to form a contact structure having a target depth.

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

Abstract: Embodiments of this application provide a method, an apparatus and a device for measuring a semiconductor structure. Before measurement of a to-be-measured semiconductor structure, a reference semiconductor structure corresponding to the to-be-measured semiconductor structure is set, and a first simulation model corresponding to the to-be-measured semiconductor structure and a second simulation model corresponding to the reference semiconductor structure are established, some structure parameters of the to-be-measured semiconductor structure have parameter values different from those of corresponding structure parameters of the reference semiconductor structure.

Abstract: Provided is a method for simulating electricity of a wafer chip. The method includes: a database is constructed, the database including spectroscopic data of a semiconductor structure of the wafer chip obtained from a target key process, actual electrical data of the wafer chip, and a correspondence between the spectroscopic data and the actual electrical data; the target key process is performed on a target wafer chip to obtain the spectroscopic data of the semiconductor structure of the target wafer chip obtained from the target key process, the spectroscopic data being target spectroscopic data; the electrical data of the target wafer chip is simulated based on the obtained target spectroscopic data and the database, the electrical data being target electrical data.

Abstract: A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer.

Abstract: A method may include generating a frequency-agnostic signal using an adjustable oscillator, and applying the frequency-agnostic signal to a user. The method may also include determining a reflecting value based on the frequency-agnostic signal as reflected by the user. The method may additionally include identifying a peak in the reflecting value by at least repeatedly comparing the determined reflecting value to a previously stored highest reflecting value, and adjusting the adjustable oscillator based on the comparison. The method may also include, after identifying the peak, determining a frequency of the oscillator corresponding to the peak, and outputting the frequency of the oscillator.

Abstract: A waste management apparatus, system, and method that includes a receiving unit having at least one anti-siphon valve, a holding section, and an analysis section. An analysis unit coupled to the analysis section, and configured to analyze a fluid for identification, concentration, and amount. At least two control valves fluidly coupled to the receiving unit, and a waste reservoir fluidly coupled to one or more of the at least two control valves. A computing device may be coupled to and control and receive signals of the analysis unit, and the at least two control valves. The receiving unit can have a first side configured for receiving a fluid transport device, the first side being fluidly coupled to a holding section of the receiving unit, and an analysis section of the receiving unit fluidly coupled to the holding section and a second side of the receiving unit.

Abstract: A sliding mechanism for a vehicle floor console is disclosed. The sliding mechanism comprises a base portion including a panel and a sliding groove, the sliding groove being positioned at the end of the panel and having an opening, and a guide portion including a guide rail disposed in the sliding groove and being slidable in the sliding groove. The sliding groove includes first and second surfaces positioned along the first direction, having angles with the first direction, connected to each other and enclosing a first sliding portion of the guide rail.

Abstract: A chip package includes a flexible substrate, a chip, a pressure-proof member and a reinforcement sheet. The chip and the pressure-proof member are located on a first surface of the flexible substrate, and the reinforcement sheet is located on a second surface of the flexible substrate. The pressure-proof member at least includes a pair of pressure-proof ribs which are located outside of the chip oppositely. The pressure-proof ribs located outside the chip can protect the chip from the damage caused by the pressure of other component (e.g. curved panel) except the chip package.

Abstract: An output circuit includes a level adjustment circuit and a determination circuit. The output circuit is employed for generating an output to an output terminal of the output circuit, where the output terminal is coupled to a connecting port. The level adjustment circuit is coupled to the output terminal and is employed for generating at least one adjusted signal according to a first voltage signal at the output terminal in a first period and a second voltage signal at the output terminal in a second period. The determination circuit is coupled to the level adjustment circuit and is employed for generating a determination signal according to the at least one adjusted signal, wherein the determination signal indicates whether a load is connected to the connecting port.