Patents by Inventor Shin-Wen LIN

Shin-Wen LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9841487
    Abstract: A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 12, 2017
    Assignee: CHROMA ATE INC.
    Inventors: Hou-Chun Chen, Shin-Wen Lin, Ching-Hua Chu, Po-Kai Cheng
  • Patent number: 9647650
    Abstract: A clock generating device includes a first timing delay module, a multiplexer, and a second timing delay module. The multiplexer is electrically connected to the first timing delay module. The second timing delay module is electrically connected to the multiplexer. The first timing delay module generates a plurality of delayed clock signals based on a reference clock signal. The multiplexer outputs a first delayed clock signal and a second delayed clock signal, among the plurality of delayed clock signals, based on a clock generating signal. The second timing delay module generates an output clock signal based on the clock generating signal, the first delayed clock signal and the second delayed clock signal.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 9, 2017
    Assignee: CHROMA ATE INC.
    Inventors: Cheng-Hsien Chang, Ching-Hua Chu, Shin-Wen Lin
  • Publication number: 20160191032
    Abstract: A clock generating device includes a first timing delay module, a multiplexer, and a second timing delay module. The multiplexer is electrically connected to the first timing delay module. The second timing delay module is electrically connected to the multiplexer. The first timing delay module generates a plurality of delayed clock signals based on a reference clock signal. The multiplexer outputs a first delayed clock signal and a second delayed clock signal, among the plurality of delayed clock signals, based on a clock generating signal. The second timing delay module generates an output clock signal based on the clock generating signal, the first delayed clock signal and the second delayed clock signal.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 30, 2016
    Inventors: Cheng-Hsien CHANG, Ching-Hua CHU, Shin-Wen LIN
  • Publication number: 20160124066
    Abstract: A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Inventors: Hou-Chun CHEN, Shin-Wen LIN, Ching-Hua CHU, Po-Kai CHENG