Abstract: A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices. The method includes programming data in a memory cell array included in the non-volatile data storage device using a page buffer selected from among a plurality of page buffers included in the non-volatile data storage device and performing a setup operation for loading data using another page buffer, which is different from the page buffer selected during the programming.

Abstract: Users of a method and apparatus to purchase (e.g., rent or buy) contents using a portable storage medium, via a network or the like. Contents purchased using embodiments of a method and apparatus may be developed to be automatically deleted or to be non-reproducible after being reproduced one time or after a predetermined period. Accordingly, users do not need to return borrowed or purchased contents. Also an owner of a contents rental shop may prevent contents from being unfairly reproduced. Further, user inconvenience due to the conventional manner in which users have to memorize information related to the contents and visit a rental shop to obtain desired contents may be avoided or decreased. Portable storage mediums or network resources of exemplary methods and apparatuses may be repeatedly used (e.g., without limitation), and thus may contribute to the saving of resources.

Abstract: A method and device for controlling commands used for a flash memory are provided. The method includes, substantially reducing usage of a central processing unit (CPU) and a bus, when controlling the flash memory, by receiving information on at least one command currently stored in a system memory, receiving a command represented by the received information from the system memory, and generating an interrupt representing that all the commands are received, when receiving of substantially all the commands represented by the received information is completed.

Abstract: A command scheduling method and apparatus for reducing the complexity of a virtual file system embodied in a nonvolatile data storage device and performing efficient interleaving by setting a preparation phase of a command schedule in the virtual file system embodied in the nonvolatile data storage device is provided. The method includes setting a preparation phase in which a plurality of metadata commands for data management are executed, and if the plurality of metadata commands are completely executed in the preparation phase, executing data read/write commands. Accordingly, by simplifying the scheduling structure of the virtual file system (FTL), code size and resource use can be reduced. In addition, by performing exact interleaving, burst data transmission between a host and a memory storage device can be achieved even without using a large capacity buffer.

Abstract: Provided are a flash memory system and a programming method performed in the flash memory system. The flash memory system includes a buffer unit including a plurality of buffers, and temporarily storing data transmitted by a host; a plurality of channel units each including at least one flash memory chip that includes a plurality of memory cell arrays; and a control unit which controls the data stored in the buffer unit to be sequentially transmitted to the channel units and the transmitted data to be recorded to the memory cell arrays of the flash memory chips in the channel units.

Abstract: A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices. The method includes programming data in a memory cell array included in the non-volatile data storage device using a page buffer selected from among a plurality of page buffers included in the non-volatile data storage device and performing a setup operation for loading data using another page buffer, which is different from the page buffer selected during the programming.

Abstract: The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined peripheral device among peripheral devices connected to the second bus for each cycle of a clock signal received from the first bus, and keeping a read state or a write state for the predetermined peripheral device by continuously outputting a read signal or a write signal for the predetermined peripheral device to the second bus, during the counting of the match value. According to the present invention, it is not necessary to operate depending on a peripheral device operating at the lowest speed among peripheral devices, and not necessary to add wrappers to the peripheral devices, by employing the AHB-to-ISA bridge variably adjusting the output times of output signals to an ISA bus.

Abstract: Provided are a multi-channel flash memory system capable of increasing the overall bandwidth by using a plurality of flash memory chips, and a programming method performed in the flash memory system. The flash memory system includes: a plurality of channel units each including at least two flash memory chips, a control unit which controls the flash memory chips, and a buffer unit which stores external data; and a host interface unit which transmits data separated according to the number of the channel units and transmitted by a host to the buffer units of the channel units, wherein the control unit records the data stored in the buffer unit into the at least two flash memory chips.

Abstract: A system-on-chip (SOC) based on an advanced micro-controller bus architecture (AMBA), and particularly, a bus connection method, is provided. The bus connection method includes: allowing one of a plurality of masters to use a plurality of slaves; generating information necessary for using the slaves by decoding a command generated by the master allowed to use the slaves; and outputting signals with reference to the generated information according to a protocol of a bus system to which the slaves are connected. Accordingly, it is possible to transmit data in a pipeline approach by applying bank interleaving to an occasion when only one master issues a request for the reading or writing of data in units of blocks.

Abstract: An apparatus and method for identifying whether a memory card is inserted and for constituting data for identifying the memory card using hardware are provided. The apparatus establishes a data transfer mode through identifying the insertion of a card and includes a card insertion identifier, a card assignment information receiver, and a data transfer mode establisher. The card insertion identifier identifies whether a card is inserted. The card assignment information receiver receives predetermined card assignment information from a card driver if the card insertion identifier identifies that the card is inserted. The data transfer mode establisher establishes the data transfer mode for the card based on the card assignment information. The apparatus further includes a data transfer mode releaser that if the card insertion identifier identifies in the data transfer mode that the card is no longer inserted, informs the card driver that the card is not inserted to release the data transfer mode.

Abstract: The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined peripheral device among peripheral devices connected to the second bus for each cycle of a clock signal received from the first bus, and keeping a read state or a write state for the predetermined peripheral device by continuously outputting a read signal or a write signal for the predetermined peripheral device to the second bus, during the counting of the match value. According to the present invention, it is not necessary to operate depending on a peripheral device operating at the lowest speed among peripheral devices, and not necessary to add wrappers to the peripheral devices, by employing the AHB-to-ISA bridge variably adjusting the output times of output signals to an ISA bus.

Abstract: Provided are a memory control apparatus and method for controlling an order of processing memory access commands from a plurality of master devices when the master devices access a memory to improve a processing speed. The memory controller includes a command queue receiving memory access commands from at least one master device and storing the memory access commands; a determination unit analyzing addresses of a memory, which will be accessed by the received commands, to control an order of processing the stored commands; and a command interpreter interpreting a command output under the control of the determination unit to output an address related signal. Accordingly, a command processing speed is remarkably improved without increasing a system size.

Abstract: An apparatus and method for controlling access to a memory to minimize a latency in a bus system when there is a wrapping burst request from a bus. The apparatus includes a first detecting unit detecting a burst length in a wrapping burst instruction received from the bus master when the command received from the bus master is the wrapping burst instruction, a second detecting unit detecting in the received wrapping burst instruction a start address of a region of the memory to be accessed when the command received from the bus master is the wrapping burst instruction, and a finite state machine (FSM) detecting an address to be wrapped based on the detection results of the first and the second detecting units and generating signals for controlling the memory to output a CAS command of the address to be wrapped.

Abstract: A command transmission method and apparatus, capable of improving command transmission efficiency by using a queue, when the queue is required during an operation of a command bus in a pipeline bus system includes determining whether a command bus of the pipeline bus system is in a busy state; and transmitting a command from the master to a target slave while selectively using a queue protocol of an arbiter of the pipeline bus system according to a result of the determination.

Abstract: An apparatus and method for identifying whether a memory card is inserted and for constituting data for identifying the memory card using hardware are provided. The apparatus establishes a data transfer mode through identifying the insertion of a card and includes a card insertion identifier, a card assignment information receiver, and a data transfer mode establisher. The card insertion identifier identifies whether a card is inserted. The card assignment information receiver receives predetermined card assignment information from a card driver if the card insertion identifier identifies that the card is inserted. The data transfer mode establisher establishes the data transfer mode for the card based on the card assignment information. The apparatus further includes a data transfer mode releaser that if the card insertion identifier identifies in the data transfer mode that the card is no longer inserted, informs the card driver that the card is not inserted to release the data transfer mode.