Patents by Inventor Shin-Yu Nieh
Shin-Yu Nieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9985105Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.Type: GrantFiled: June 30, 2016Date of Patent: May 29, 2018Assignee: Nanya Technology CorporationInventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
-
Publication number: 20160351678Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.Type: ApplicationFiled: June 30, 2016Publication date: December 1, 2016Inventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
-
Patent number: 8912065Abstract: A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.Type: GrantFiled: June 15, 2012Date of Patent: December 16, 2014Assignee: Nanya Technology CorporationInventors: Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Shin-Yu Nieh
-
Publication number: 20140264640Abstract: The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: NANYA TECHNOLOGY CORP.Inventors: Shin-Yu Nieh, Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee
-
Publication number: 20130337629Abstract: A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Shin-Yu Nieh
-
Patent number: 8183614Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.Type: GrantFiled: November 11, 2011Date of Patent: May 22, 2012Assignee: Nanya Technology CorporationInventor: Shin-Yu Nieh
-
Publication number: 20120056301Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.Type: ApplicationFiled: November 11, 2011Publication date: March 8, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventor: SHIN-YU NIEH
-
Patent number: 8084323Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.Type: GrantFiled: December 17, 2009Date of Patent: December 27, 2011Assignee: Nanya Technology CorporationInventor: Shin-Yu Nieh
-
Patent number: 8043884Abstract: A method for seamless gap filling is provided, including providing a semiconductor structure with a device layer having a gap therein, wherein the gap has an aspect ratio greater than 4. A liner layer is formed over the device layer exposed by the gap. A first un-doped oxide layer is formed over the liner layer in the gap. A doped oxide layer is formed over the first undoped oxide layer in the gap. A second un-doped oxide layer is formed over the doped oxide layer in the gap to fill the gap. An annealing process is performed on the second un-doped oxide layer, the doped oxide layer, and the first un-doped oxide to form a seamless oxide layer in the gap, wherein the seamless oxide layer has an interior doped region.Type: GrantFiled: May 24, 2010Date of Patent: October 25, 2011Assignee: Nanya Technology CorporationInventors: Shin-Yu Nieh, Shuo-Che Chang, Hui-Lan Chang, Cheng-Shun Chen
-
Publication number: 20110147887Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: NANYA TECHNOLOGY CORPORATIONInventor: Shin-Yu Nieh
-
Publication number: 20100310790Abstract: A method of forming a carbon-containing layer is provided. First, a substrate having a target layer thereon is provided. Next, a plasma containing CxHyFz is generated. Thereafter, a plasma deposition process is performed to the substrate by using the plasma containing CxHyFz so as to form the carbon-containing layer on the target layer.Type: ApplicationFiled: June 9, 2009Publication date: December 9, 2010Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Shuo-Che Chang, Shin-Yu Nieh
-
Publication number: 20100172065Abstract: A capacitor structure includes: a top electrode, a bottom electrode, a first capacitor dielectric layer positioned between the top electrode and the bottom electrode and a second capacitor dielectric layer positioned between the top electrode and the bottom electrode. The first capacitor dielectric layer is selected from the group consisting HfO2, ZrO2, and TiO2. The second capacitor dielectric layer is selected from the group consisting of lanthanide oxide series and rare earth oxide series.Type: ApplicationFiled: March 6, 2009Publication date: July 8, 2010Inventors: Tsai-Yu Huang, Shin-Yu Nieh, Hui-Lan Chang
-
Patent number: 7666792Abstract: The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.Type: GrantFiled: February 22, 2008Date of Patent: February 23, 2010Assignee: Nanya Technology Corp.Inventors: Chung-Yen Chou, Hai-Han Hung, Teng-Wang Huang, Shin-Yu Nieh
-
Publication number: 20100006954Abstract: A transistor device includes a semiconductor substrate, a source doping region and a drain doping region in the semiconductor, a channel region between the source doping region and the drain doping region, a gate stack on the channel region, wherein the gate stack includes an amorphous interfacial layer, a crystalline metal oxide gate dielectric layer and a gate conductor.Type: ApplicationFiled: September 30, 2008Publication date: January 14, 2010Inventors: Tsai-Yu Huang, Shin-Yu Nieh, Hui-Lan Chang
-
Publication number: 20090311878Abstract: A depositing method for a dielectric material is provided, where the dielectric material has the first and the second primary elements, and a single precursor includes the first and the second primary elements. The depositing method includes pulsing the single precursor, purging a redundant part of the single precursor, pulsing an oxidant for oxidizing the single precursor, and purging a redundant part of the oxidant.Type: ApplicationFiled: August 26, 2008Publication date: December 17, 2009Applicant: NANYA TECHNOLOGY CORP.Inventors: Shin-Yu Nieh, Tsai-Yu Huang, Chun-I Hsieh
-
Publication number: 20090283856Abstract: A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a metal oxy-nitride layer acting as a capacitor dielectric layer of the capacitor device. A top electrode layer is then formed on the metal oxy-nitride layer.Type: ApplicationFiled: July 2, 2008Publication date: November 19, 2009Inventors: Tsai-Yu Huang, Shin-Yu Nieh, Chun-I Hsieh
-
Publication number: 20090130853Abstract: The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.Type: ApplicationFiled: February 22, 2008Publication date: May 21, 2009Inventors: Chung-Yen Chou, Hai-Han Hung, Teng-Wang Huang, Shin-Yu Nieh