Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: A multiplier for obtaining the product of elements in a Galois Field. The multiplier performs the multiplication of two n-bit elements, A(an-1, an-2, . . . , a3, a2, a1, a0) and B(bn-1, bn-2, . . . , b3, b2, b1, b0) in the Galois Field to yield the product C(cn-1, cn-2, . . . , c3, c2, c1, c0), wherein n≧1 ai(i=0˜n-1), bj(j=0˜n-1), and ck(k=O˜n-1) are all binary bits. The multiplier includes: an AND planer, for performing an AND logic operation of every bit ai in A(an-1, an-2, . . . , a3, a2, a1, a0) and every bit bj in B(bn-1, bn-2, . . . , b3, b2, b1, b0) to obtain (an-1bn-1, an-1bn-2, . . . , an-1b0, an-2bn-1, an-2bn-2, . . . , an-2b0, a0bn-1, a0bn-2, . . . , a0b0); and an XOR planer, for performing an XOR logic operation of the output from the AND planer to obtain C(cn-1, cn-2, . . . , c3, c2, c1, c0).

Abstract: A means and a method applied in syndrome generation in the Video/Audio processing system is disclosed. The syndromes thereof are effectively and rapidly generated simply using shift register and an exclusive or adder by a recursive operation. For the code words having a number of bytes, the syndromes can be generated by repeating exclusive or (XOR) operation between a shift bit and the above-mentioned bytes, without the extra step of table-matching, saving large memory capacity, greatly reducing the operation cycle and completing the operation rapidly.

Abstract: A table matching method for multiplication of elements in Galois Field. First, a table of the byte value in Galois Field and the corresponding exponent is formed in the hardware. To perform the multiplication between two elements in the Galois Field, the corresponding exponents of the two elements are found out in advance. The two exponents are then added up to obtain a sum. Then, by using the table, a corresponding byte value of the sum can be obtained. The byte value is the product of the two elements in the Galois Field.

Abstract: A decoding device for deinterleaving data includes a write address generator, a read address generator, and a memory device. According to a method for deinterleaving data, the write address generator generates a write address according to parameters corresponding to the interleaving characteristics of an input signal. The write addresses are offset according to the parameters in order to apply a deinterleaving function to the input data. The read address generator generates a read address so as to sequentially read the stored data, to provide deinterleaved output data.