Abstract: An OTP with ultra-low power read can be programmed with a minimum and a maximum program voltage. When programming within the range, the post-program OTP to pre-program resistance ratio can be larger than N, where N>50, so that more sensing techniques, such as single-end sensing, can be used to reduce read current. At least one of the OTP cells can be coupled to a common bitline, which can be further coupled to a first supply voltage lines via a plurality of datalines. The resistance in the at least one OTP cell can be evaluated by strobing at least one comparator output of the discharging bitline/dataline.

Abstract: An electronic device and method of generating a Physically Unclonable Function (“PUF”) value is disclosed. An OTP memory with a plurality of OTP cells that can be reliably and deterministically programmed with a minimum and a maximum program voltage being selected for pre-conditioning. All OTP cells can be programmed at least once around the minimum program voltage to hide the program status. Data to be programmed into the OTP can be a fixed, time-varying voltage or data from an entropy source. The programmed OTP data can be masked for weak bits and further randomized to generate PUF output by compressing a bit stream into a single bit, e.g., single parity bit. The PUF output can be through a hash function and/or to generate keys.

Abstract: Programmable resistive memory can be integrated with wide-bandgap semiconductor devices on a wide-bandgap semiconductor, silicon, or insulator substrate. The wide-bandgap semiconductor can be group IV-IV, III-V, or II-VI crystal or compound semiconductor, such as silicon carbide or gallium nitride. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a metal, silicon, polysilicon, silicided polysilicon, or thermally insulated wide-bandgap semiconductor. The selector in a programmable resistive memory can be a MOS or diode fabricated by wide-bandgap semiconductor.

Abstract: An OTP with ultra-low power read can be programmed with a minimum and a maximum program voltage. When programming within the range, the post-program OTP to pre-program resistance ratio can be larger than N, where N>50, so that more sensing techniques, such as single-end sensing, can be used to reduce read current. At least one of the OTP cells can be coupled to a common bitline, which can be further coupled to a first supply voltage lines via a plurality of datalines. The resistance in the at least one OTP cell can be evaluated by strobing at least one comparator output of the discharging bitline/dataline.

Abstract: A time-based sensing circuit to convert resistance of a one-time programmable (OTP) element into logic states is disclosed. A one-time programmable (OTP) memory has a plurality of OTP devices. At least one of the OTP devices can have at least one OTP element that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the OTP element resistance into a logic state.

Abstract: An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region. The first active region can be doped with a first type of dopant and the second active region can be doped with a first or second type of dopant. The OTP element can be coupled to the first active region with the other end coupled to a first supply voltage line. The second active region can be coupled to a second voltage supply line and the MOS gate is coupled to a third voltage supply line.

Abstract: A method of testing an OTP memory is disclosed. An OTP program mechanism that uses heat accelerated electromigration can be fully tested. In one embodiment, an OTP cell's programmability can be tested if an initial OTP element resistance is less than a predetermined resistance, as such insures that sufficient heat can be generated to be programmable. A non-destructive program state, or fake reading 1, can be created by low-voltage programming a cell while reading the same cell at the same time. Accordingly, alternative 0s and 1s patterns can be generated to fully test every functional block of an OTP memory.

Abstract: Programmable resistive memory can be fabricated with a non-single-crystalline silicon formed on a flexible substrate. The non-single-crystalline silicon can be amorphous silicon, low-temperature polysilicon (LTPS), organic semiconductor, or metal oxide semiconductor. The flexible substrate can be glass, plastics, paper, metal, paper, or any kinds of flexible film. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a silicon, polysilicon, organic or metal oxide electrode. The selector in a programmable resistive memory can be a MOS or diode with top gate, bottom gate, inverted, staggered, or coplanar structures.

Abstract: A time-based sensing circuit to convert resistance of a one-time programmable (OTP) element into logic states is disclosed. A one-time programmable (OTP) memory has a plurality of OTP devices. At least one of the OTP devices can have at least one OTP element that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the OTP element resistance into a logic state.

Abstract: Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.

Abstract: A time-based sensing circuit to convert resistance of a programmable resistive element into logic states is disclosed. A programmable resistive memory has a plurality of programmable resistive devices. At least one of the programmable resistive devices can have at least one programmable resistive element (PRE) that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the PRE resistance into a logic state.

Abstract: Programmable resistive memory can be fabricated with a non-single-crystalline silicon formed on a flexible substrate. The non-single-crystalline silicon can be amorphous silicon, low-temperature polysilicon (LTPS), organic semiconductor, or metal oxide semiconductor. The flexible substrate can be glass, plastics, paper, metal, paper, or any kinds of flexible film. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a silicon, polysilicon, organic or metal oxide electrode. The selector in a programmable resistive memory can be a MOS or diode with top gate, bottom gate, inverted, staggered, or coplanar structures.

Abstract: An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region. The first active region can be doped with a first type of dopant and the second active region can be doped with a first or second type of dopant. The OTP element can be coupled to the first active region with the other end coupled to a first supply voltage line. The second active region can be coupled to a second voltage supply line and the MOS gate is coupled to a third voltage supply line.

Abstract: Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.

Abstract: An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on a common well or on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region.

Abstract: A programmable resistive memory has a plurality of programmable resistive devices (PRD) and at least one sensing circuit. The at least one of the programmable resistive device can include at least one programmable resistive element (PRE). The sensing circuit can include one PRD unit and a reference unit. Each unit has at least one capacitor to charge to a second supply voltage line and to discharge to the first supply voltage line through the PRE and the reference element, respectively. The capacitors are also coupled to comparators to monitor discharging voltages with respect to a reference voltage. By comparing the time difference when the comparators change their outputs, the magnitude of the PRE resistance with respect to the reference element resistance can be determined and converted into logic states.

Abstract: A time-based sensing circuit to convert resistance of a programmable resistive element into logic states is disclosed. A programmable resistive memory has a plurality of programmable resistive devices. At least one of the programmable resistive devices can have at least one programmable resistive element (PRE) that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the PRE resistance into a logic state.

Abstract: A method of testing an OTP memory is disclosed. An OTP program mechanism that uses heat accelerated electromigration can be fully tested. In one embodiment, an OTP cell's programmability can be tested if an initial OTP element resistance is less than a predetermined resistance, as such insures that sufficient heat can be generated to be programmable. A non-destructive program state, or fake reading 1, can be created by low-voltage programming a cell while reading the same cell at the same time. Accordingly, alternative 0s and 1s patterns can be generated to fully test every functional block of an OTP memory.

Abstract: An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on a common well or on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region.

Abstract: Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.