Patents by Inventor Shing-Chung Tang

Shing-Chung Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same
    Patent number: 8219879
    Abstract: A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: July 10, 2012
    Assignee: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chien-Ming Wu, Ming-Der Shieh, Chun-Ming Huang, Chi-Sheng Lin, Shih-Hao Fang, Shing-Chung Tang
  • METHOD FOR ARRANGING MEMORIES OF LOW-COMPLEXITY LDPC DECODER AND LOW-COMPLEXITY LDPC DECODER USING THE SAME
    Publication number: 20110138248
    Abstract: A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.
    Type: Application
    Filed: February 18, 2010
    Publication date: June 9, 2011
    Applicant: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chien-Ming Wu, Ming-Der Shieh, Chun-Ming Huang, Chi-Sheng Lin, Shih-Hao Fang, Shing-Chung Tang