Abstract: Subcarrier multiplexed acknowledgment tones are used for contention recovery in multiple-access WDM networks with basedband data packets and subcarrier multiplexed control headers. Upon receiving a data message from another node, the receiving node sends a subcarrier acknowledgement tone to the transmitter thus informing the transmitting node that the message has been received. The thoughput of the network is significantly improved. In an alternative embodiment, an acknowledgement is sent from the receiver by impressing a data message on a subcarrier.

Abstract: An optical memory cell constructed from an optical combiner, a 1.times.2 optical swtich and optical fibers. One input port of the optical combiner serves as the input to the memory cell. The output port of the optical combiner is connected to the input of the optical switch by an optical fiber. A first output port of said switch is connected by an optical fiber to the second input of the optical combiner, such that when said switch is in the straight-through state, an optical loop is formed through which an optical pulse can circulate. The second output of the optical switch serves as the output of the memory cell when said optical switch is in the cross-over state. Control signals are provided by a clock.

Abstract: An optical serial-to-parallel converter constructed from at least two optical shift registers connected in cascade, each optical shift register having a 1.times.2 optical switch connected to its output. Each optical shift register in the sequence is optically coupled to the next sequential optical shift register through one output of said 1.times.2 optical switch to the input port of the next sequential optical shift register. The input port of the first optical shift register serves as the input to the optical serial-to-parallel converter, receiving a series of optical pulses. The output ports of each of said third optical switches serve as the output ports of the optical serial-to-parallel converter. The optical shift registers are controlled by two clocks, operating at the same rate, but each out of phase with the other.

Abstract: An optical parallel-to-serial converter constructed from at least two optical shift registers coupled in cascade by an optical two-to-one combiner. The input port of the first optical shift register serves as one input to the parallel-to-serial converter, an extra optical combiner optically coupled to the last of said optical shift registers serves as one input port, while the optical combiners coupling said optical shift registers serve as the other input ports receiving parallel optical pulses. The output port of the last of said cascaded optical shift registers serves as the output port of the parallel-to-serial converter. The shift registers are controlled by two clocks, operating at the same rate, but each out of phase with the other, providing control signals to shift and output said optical pulses serially from said shift registers to effect a parallel-to-serial conversion.

Abstract: A 1.times.2 integrated optical switch with a high extinction ratio is obtained from the monolithic integration of three integrated waveguide couplers. The waveguide couplers are designed such that the output of the first waveguide coupler is directly coupled to the input of the other two integrated waveguide couplers by an integrated waveguide. Thus, the switch has two cascaded integrated waveguide couplers along each path from the single input to each of the two outputs. Only two pairs of electrodes are required by this design. The extinction ratio of this switch is the sum of the extinction ratios along an input-output path. Since integrated waveguide couplers are bidirectional, this switch can be used as a 2.times.1 switch by reversing the input and outputs.

Abstract: An optical shift register constructed from at least two optical memory cells connected in cascade, each memory cell having an optical combiner, a 1.times.2 optical switch, a clock, and an optical amplifier, all connected by optical fibers. Each memory cell in the sequence is connected to the next sequential cell by an optical fiber from its output port to the input port of the next sequential cell. The input port of the first optical memory cell serves as the input to the shift register. The output port of the last sequential optical memory cell serves as the output port of the shift register. Each cell is controlled by a clock, all clocks operating at the same rate, but each out of phase with the clock in the next sequential cell. Control signals are provided by said clocks to shift optical pulses from one cell to the next for the enter-shift-exit cycle of the shift register.

Abstract: An optical time slot interchanger which interchanges one optical pulse at a time in a bit interleaved format. The optical time slot interchanger is constructed from an N-bit serial-to-parallel converter and N optical memory cells, each of said optical memory cells being optically coupled to a parallel output port of said optical-to-serial converter. The ouputs of all N optical memory cells are optically coupled to form a single output port for the time slot interchanger. The optical time slot interchanger has a single input port to receive serially a frame of N optical pulses and a single output to present serially said frame of pulses with interchanged time slots. As a frame of N optical pulses enters the optical time slot interchanger, they are shifted and stored in said optical serial-to-parallel converter under the control of clock means. The optical pulses are then shifted to optical memory cells to await serial output in a time slot interchange under control of other clock signals.