Abstract: A dual vertical channel transistor includes a tuning fork-shaped substrate body; a buried bit line embedded at a bottom of a recess between two prong portions of the tuning fork-shaped substrate body; an out-diffused drain region adjacent to the buried bit line in the tuning fork-shaped substrate body; a source region situated at a top portion of each of the two prong portions of the tuning fork-shaped substrate body; an epitaxial portion connecting the two prong portions of the tuning fork-shaped substrate body between the out-diffused drain region and the source region; a front gate situated on a first side surface of the tuning fork-shaped substrate body; and a back gate situated on a second side surface opposite to the first side surface of the tuning fork-shaped substrate body.

Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.

Abstract: A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position between the top wafer and the bottom wafer so that the top mark and the bottom mark are in contact with each other; applying an electrical signal on the top mark to obtain an electrical reading and optimizing the electrical reading to substantially align the wafer stack.

Abstract: An isolation structure is described, including a doped semiconductor layer disposed in a trench in a semiconductor substrate and having the same conductivity type as the substrate, gate dielectric between the doped semiconductor layer and the substrate, and a diffusion region in the substrate formed by dopant diffusion through the gate dielectric from the doped semiconductor layer. A device structure is also described, including the isolation structure and a vertical transistor in the substrate beside the isolation structure. The vertical transistor includes a first S/D region beside the diffusion region and a second S/D region over the first S/D region both having a conductivity type different from that of the doped semiconductor layer.

Abstract: An isolation structure is described, including a doped semiconductor layer disposed in a trench in a semiconductor substrate and having the same conductivity type as the substrate, gate dielectric between the doped semiconductor layer and the substrate, and a diffusion region in the substrate formed by dopant diffusion through the gate dielectric from the doped semiconductor layer. A device structure is also described, including the isolation structure and a vertical transistor in the substrate beside the isolation structure. The vertical transistor includes a first S/D region beside the diffusion region and a second S/D region over the first S/D region both having a conductivity type different from that of the doped semiconductor layer.

Abstract: An integrated circuit device includes a semiconductor substrate having a first region and second region, a conductive via positioned in the first region of the semiconductor substrate, at least one active element positioned in the second region of the semiconductor substrate, a conductive layer extending from the first region to the second region and electrically connecting the conductive via to the active element, and an auxiliary structure positioned in the first region of the semiconductor substrate and proximate to the conductive via. The auxiliary structure can be a stress-absorbing structure, and the volume of the stress-absorbing structure decreases as the volume of the conductive via increases. The auxiliary structure can be a heat-evacuating structure, and the heat-evacuating structure is configured to transfer the operating heat generated by the active element from the first region of the semiconductor substrate to the conductive via through the conductive layer.

Abstract: An integrated circuit device includes a semiconductor substrate having a first region and second region, a conductive via positioned in the first region of the semiconductor substrate, at least one active element positioned in the second region of the semiconductor substrate, a conductive layer extending from the first region to the second region and electrically connecting the conductive via to the active element, and an auxiliary structure positioned in the first region of the semiconductor substrate and proximate to the conductive via. The auxiliary structure can be a stress-absorbing structure, and the volume of the stress-absorbing structure decreases as the volume of the conductive via increases. The auxiliary structure can be a heat-evacuating structure, and the heat-evacuating structure is configured to transfer the operating heat generated by the active element from the first region of the semiconductor substrate to the conductive via through the conductive layer.

Abstract: A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position between the top wafer and the bottom wafer so that the top mark and the bottom mark are in contact with each other; applying an electrical signal on the top mark to obtain an electrical reading and optimizing the electrical reading to substantially align the wafer stack.

Abstract: An integrated circuit structure includes a semiconductor substrate, an active device disposed on a first region of the semiconductor substrate, a layer stack disposed on a second region of the semiconductor substrate, a through via penetrating through the layer stack and the semiconductor substrate, and a third dielectric layer disposed between the through via and the semiconductor substrate. In one embodiment of the present invention, the layer stack includes a first dielectric layer disposed on the semiconductor substrate and a heat-conducting member disposed on the first dielectric layer.

Abstract: An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple pads disposed on a top wafer and having first pads and second pads, and a monitoring via electrically connected to the first pads. The bottom mark includes a first bottom pad corresponding to the monitoring via and a second bottom pad corresponding to the second pads. Further the first bottom pad and the second bottom pad are electrically connected to each other so that the monitoring via may be electrically connected to the second pads by means of the first bottom pad when the top mark and the bottom mark are aligned with each other.

Abstract: A flash memory cell according to the present invention includes a first charge-trapping region and a second charge-trapping region disposed in a semiconductor substrate, a first doped region disposed in the semiconductor substrate at a first side of the first charge-trapping region, a second doped region disposed in the semiconductor substrate at a second side of the first charge-trapping region, a first dielectric layer separating the semiconductor substrate from the first charge-trapping region and the second charge-trapping region, a first conductor disposed above the first charge-trapping region, and a second dielectric layer separating the first charge-trapping region from the first conductor, wherein the second charge-trapping region is configured to influence the conduction behavior of a carrier channel in the semiconductor substrate under the first charge-trapping region.

Abstract: A single-gate FinFET structure includes an active fin structure having two enlarged head portions and two respective tapered neck portions that connect the enlarged head portions with an underlying ultra-thin body. Two source/drain regions are doped in the two enlarged head portions respectively. An insulation region is interposed between the two source/drain regions. A trench isolation structure is disposed at one side of the tuning fork-shaped fin structure. A single-sided sidewall gate electrode is disposed on a vertical sidewall of the active fin structure opposite to the trench isolation structure.

Abstract: A semiconductor memory device positioned on an SOI substrate. A semiconductor memory device includes two transistors with three terminals which serve as a source, a reading drain and a writing drain, respectively. The writing drain is heavily-doped for high writing efficiency. A floating body region for storing charges is also heavily-doped to reach long data retention time.

Abstract: A method for fabricating a through-substrate via structure. A semiconductor substrate is provided. A first via hole is etched into the semiconductor substrate. A spacer is formed on sidewall of the first via hole. The semiconductor substrate is etched through the first via hole to form a second via hole. The second via hole is wet etched to form a bottle-shaped via hole. An insulating layer is formed lining a lower portion of the bottle-shaped via hole. A first conductive layer is deposited within the bottle-shaped via hole, wherein the first conductive layer define a cavity. A bond pad is formed on a front side of the semiconductor substrate, wherein the bond pad is electrically connected with the first conductive layer. A back side of the semiconductor substrate is polished to reveal the cavity. The cavity is filled with a second conductive layer.

Abstract: An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple pads disposed on a top wafer and having first pads and second pads, and a monitoring via electrically connected to the first pads. The bottom mark includes a first bottom pad corresponding to the monitoring via and a second bottom pad corresponding to the second pads. Further the first bottom pad and the second bottom pad are electrically connected to each other so that the monitoring via maybe electrically connected to the second pads by means of the first bottom pad when the top mark and the bottom mark are aligned with each other.

Abstract: A semiconductor memory device positioned on an SOI substrate. A semiconductor memory device includes two transistors with three terminals which serve as a source, a reading drain and a writing drain, respectively. The writing drain is heavily-doped for high writing efficiency. A floating body region for storing charges is also heavily-doped to reach long data retention time.

Abstract: A dual vertical channel transistor includes a tuning fork-shaped substrate body; a buried bit line embedded at a bottom of a recess between two prong portions of the tuning fork-shaped substrate body; an out-diffused drain region adjacent to the buried bit line in the tuning fork-shaped substrate body; a source region situated at a top portion of each of the two prong portions of the tuning fork-shaped substrate body; an epitaxial portion connecting the two prong portions of the tuning fork-shaped substrate body between the out-diffused drain region and the source region; a front gate situated on a first side surface of the tuning fork-shaped substrate body; and a back gate situated on a second side surface opposite to the first side surface of the tuning fork-shaped substrate body.

Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

Abstract: A transistor device employed in a support circuit of a DRAM includes a semiconductor substrate having thereon a gate trench, a recessed gate embedded in the gate trench, a source doping region disposed at one side of the recessed gate, a drain doping region disposed at the other side of the recessed gate, and a gate dielectric layer between the recessed gate and the semiconductor substrate. The gate dielectric layer has at least two thicknesses that render the high-voltage transistor device asymmetric. The thicker gate dielectric layer is between the recessed gate and the drain doping region, while the thinner gate dielectric layer is between the recessed gate and the source doping region.