Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.

Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.

Abstract: The disclosure generally relates to a method for method for plasma etching a substrate in a plasma reactor comprising positioning the substrate on an electrostatic chuck inside the plasma reactor; supplying a DC voltage to the chuck, the DC voltage forming an electrostatic charge buildup on the substrate; plasma etching the substrate; disconnecting the DC voltage to the chuck; and counteracting the electrostatic charge buildup on the substrate by discharging a varying RF signal within the chamber.

Abstract: A method of improving the yield and performance of IC devices fabricated on a semiconductor wafer is disclosed. The method includes fabricating via plugs in via openings provided in an intermetal dielectric (IMD) layer on a wafer, subjecting the wafer to CMP to isolate the via plugs, immersing and soaking the wafer in deionized (DI) water, and drying the wafer using isopropyl alcohol, typically in a Marangoni-type dryer. The Marangoni IPA drying step prevents the formation of static electricity on the wafer, and thus, prevents the adherence of small charged particles to the wafer. As a result, the yield of IC devices fabricated on the wafer, as well as the performance of the devices, is enhanced.

Abstract: Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a blanket aluminum containing conductor layer. There is then formed over the blanket aluminum containing conductor layer a masking layer. There is then etched, while employing a plasma etch method, the blanket aluminum containing conductor layer to form a patterned aluminum containing conductor layer while employing the masking layer as an etch mask layer, where the plasma etch method employs an etchant gas composition comprising at least one fluorine containing etchant gas and at least one halogen containing etchant gas other than a fluorine containing etchant gas. There is then formed contacting the patterned aluminum containing conductor layer a conformal dielectric liner layer. There is then formed upon the conformal dielectric liner layer a spin-on-glass (SOG) planarizing layer.

Abstract: The present invention discloses a method for forming DRAM stacked capacitors by utilizing a densified oxide layer as an etch-stop for the wet etching process of an upper oxide layer in forming a contact hole for the stacked capacitor and thus, eliminating the need of a silicon nitride etch-stop layer and the occurrence of numerous processing difficulties normally observed in such stacked capacitor forming process. The lower oxide layer can be formed by a BPTEOS chemistry while the upper oxide layer can be formed by an ozone-TEOS chemistry.

Abstract: A method is described which uses the differential etch behaviour of two different kinds of sequentially deposited silicon oxide layers in conjunction with controlled thicknesses and etching conditions to allow the etching of features such as via contact holes, oxide sidewalls, and crossover insulation edges to produce non-abrupt step height profiles for better edge coverage while still maintaining close adherence to minimum spacing design ground rules between adjacent features.

Abstract: A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas.

Abstract: A method for avoiding oxide peeling by removing polymer contaminants from the edge of a wafer is described. An interlevel dielectric sandwich layer is formed by depositing a first oxide layer overlying semiconductor device structures in and on a semiconductor substrate, coating a spin-on-glass layer overlying the first oxide layer and rinsing the spin-on-glass layer whereby an edge bead rinse hump is formed a first distance from the edge of the wafer, etching back the spin-on-glass layer wherein the wafer is held by a clamp a second distance from the edge of the wafer wherein the second distance is smaller than the first distance and wherein the etching back of the spin-on-glass layer forms the polymer on the surface of the first oxide layer under the clamp at a third distance between the first and second distances, and depositing a second oxide layer overlying the etched back spin-on-glass layer and the polymer at the edge of the wafer to complete the interlevel dielectric sandwich layer.